Alessandra Nardi
Alessandra Nardi
Cadence Design Systems
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Analysis of the impact of process variations on clock skew
S Zanella, A Nardi, A Neviani, M Quarantelli, S Saxena, C Guardiani
IEEE Transactions on Semiconductor Manufacturing 13 (4), 401-407, 2000
682000
Logic synthesis for manufacturability
A Nardi, AL Sangiovanni-Vincentelli
IEEE Design & Test of Computers 21 (3), 192-199, 2004
372004
Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
A Nardi, A Neviani, E Zanoni, M Quarantelli, C Guardiani
IEEE Transactions on Semiconductor Manufacturing 12 (4), 396-402, 1999
331999
Degradation mechanisms in polysilicon emitter bipolar junction transistors for digital applications
L Vendrame, P Pavan, G Corva, A Nardi, A Neviani, E Zanoni
Microelectronics Reliability 40 (2), 207-230, 2000
292000
Synthesis for manufacturability: A sanity check
A Nardi, AL Sangiovanni-Vincentelli
Design, Automation and Test in Europe Conference and Exhibition, 2004 …, 2004
282004
Functional Safety Methodologies for Automotive Applications
A Nardi, A Armato
IEEE International Conference on Computer Aided Design (ICCAD), 956-961, 2017
212017
A methodology for the computation of an upper bound on nose current spectrum of CMOS switching activity
A Nardi, H Zeng, JL Garrett, L Daniel, AL Sangiovanni-Vincentelli
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided …, 2003
192003
Lithography aware leakage analysis
E Tuncer, H Zheng, V Raghavan, A Devgan, A Ajami, A Nardi, T Lin, ...
US Patent 8,572,523, 2013
182013
Statistical on-chip variation timing analysis
A Adams, A Nardi
US Patent 8,307,317, 2012
182012
Timing analysis using statistical on-chip variation
A Adams, A Nardi
US Patent 7,992,114, 2011
152011
Aggregate sensitivity for statistical static timing analysis
E Tuncer, A Nardi, SR Naidu, A Antonau
US Patent 7,458,049, 2008
152008
Use of statistical timing analysis on real designs
A Nardi, E Tuncer, S Naidu, A Antonau, S Gradinaru, T Lin, J Song
Proceedings of the conference on Design, automation and test in Europe, 1605 …, 2007
132007
Analysis of the impact of intra-die variance on clock skew
S Zanella, A Nardi, M Quarantelli, A Neviani, C Guardiani
Statistical Metrology, 1999. IWSM. 1999 4th International Workshop on, 14-17, 1999
121999
Lithography aware timing analysis
E Tuncer, H Zheng, V Raghavan, A Devgan, A Ajami, A Nardi, T Lin, ...
US Patent 8,473,876, 2013
82013
Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors
A Neviani, P Pavan, A Nardi, A Chantre, L Vendrame, E Zanoni
IEEE Transactions on Electron Devices 44 (11), 2059-2063, 1997
81997
Realistic worst-case modeling by performance level principal component analysis
A Nardi, A Neviani, C Guardiani
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First …, 2000
22000
Comparison of Synchronous and Asynchronous Designs For a Maximum A-Posterior Probability Decoder Memory Block
I Mavroidis, A Nardi, E Yeo
EE241 Midterm Report, University of California, Berkeley, CA, Spring, 2000
12000
Lithography aware leakage analysis
E Tuncer, H Zheng, V Raghavan, A Devgan, A Ajami, A Nardi, T Lin, ...
US Patent 9,576,098, 2017
2017
A Comparison of Synchronous and Asynchronous design
I Mavroidis, A Nardi, E Yeo
Aconstraint-DRIVEN METHODOLOGY FOR IP-BASED DESIGN OF MIXED-SIGNAL SYSTEMS INCLUDING RF COMPONENTS
AL Sangiovanni-Vincentelli, L Daniel, F De Bernardinis, A Nardi
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