| BAG2: A process-portable framework for generator-based AMS circuit design E Chang, J Han, W Bae, Z Wang, N Narevsky, B Nikolic, E Alon 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 158 | 2018 |
| A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS W Bae, H Ju, K Park, SY Cho, DK Jeong IEEE Journal of Solid-State Circuits 51 (10), 2357 - 2367, 2016 | 82 | 2016 |
| An error-free 1 Tbps WDM optical I/O chiplet and multi-wavelength multi-port laser M Wade, E Anderson, S Ardalan, W Bae, B Beheshtian, S Buchbinder, ... Optical Fiber Communication Conference, F3C. 6, 2021 | 81 | 2021 |
| CMOS Inverter as Analog Circuit: An Overview W Bae Journal of Low Power Electronics and Applications 9 (3), 26, 2019 | 57 | 2019 |
| A 22 to 26.5 Gb/s optical receiver with all-digital clock and data recovery in a 65 nm CMOS process SH Chu, W Bae, GS Jeong, S Jang, S Kim, J Joo, G Kim, DK Jeong IEEE Journal of Solid-State Circuits 50 (11), 2603-2612, 2015 | 55 | 2015 |
| Double‐Layer‐Stacked One Diode‐One Resistive Switching Memory Crossbar Array with an Extremely High Rectification Ratio of 109 KJ Yoon, GH Kim, S Yoo, W Bae, JH Yoon, TH Park, DE Kwon, YJ Kwon, ... Advanced Electronic Materials 3 (7), 1700152, 2017 | 52 | 2017 |
| A 6.7–11.2 Gb/s, 2.25 pJ/bit, single-loop referenceless CDR with multi-phase, oversampling PFD in 65-nm CMOS K Park, W Bae, J Lee, J Hwang, DK Jeong IEEE Journal of Solid-State Circuits 53 (10), 2982-2993, 2018 | 42 | 2018 |
| A crossbar resistance switching memory readout scheme with sneak current cancellation based on a two-port current-mode sensing W Bae, KJ Yoon, CS Hwang, DK Jeong Nanotechnology 27 (48), 485201, 2016 | 37 | 2016 |
| Comprehensive Writing Margin Analysis and its Application to Stacked one Diode‐One Memory Device for High‐Density Crossbar Resistance Switching Random Access Memory KJ Yoon, W Bae, DK Jeong, CS Hwang Advanced Electronic Materials 2 (10), 1600326, 2016 | 37 | 2016 |
| LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies J Han, W Bae, E Chang, Z Wang, B Nikolić, E Alon IEEE Transactions on Circuits and Systems I: Regular Papers 68 (3), 1012-1022, 2021 | 36 | 2021 |
| Teraphy: An o-band wdm electro-optic platform for low power, terabit/s optical i/o C Sun, D Jeong, M Zhang, W Bae, C Zhang, P Bhargava, D Van Orden, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 33 | 2020 |
| Review of CMOS integrated circuit technologies for high-speed photo-detection GS Jeong, W Bae, DK Jeong Sensors 17 (9), 1962, 2017 | 31 | 2017 |
| A 0.36 pJ/bit, 0.025 mm, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology W Bae, GS Jeong, K Park, SY Cho, Y Kim, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 63 (9), 1393-1403, 2016 | 31 | 2016 |
| A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection SY Cho, S Kim, MS Choo, HG Ko, J Lee, W Bae, DK Jeong IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2691-2702, 2018 | 29 | 2018 |
| A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection SY Cho, S Kim, MS Choo, J Lee, HG Ko, S Jang, SH Chu, W Bae, Y Kim, ... ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 26 | 2015 |
| A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant-Gm Bias GS Jeong, SH Chu, Y Kim, S Jang, S Kim, W Bae, SY Cho, H Ju, ... IEEE Journal of Solid-State Circuits 51 (10), 2312 - 2327, 2016 | 25 | 2016 |
| A 32 Gb/s, 201 mW, MZM/EAM cascode push–pull CML driver in 65 nm CMOS J Hwang, GS Jeong, W Bae, JE Park, CS Yoon, JM Yoon, J Joo, G Kim, ... IEEE Transactions on Circuits and Systems II: Express Briefs 65 (4), 436-440, 2017 | 24 | 2017 |
| Reference spur reduction techniques for a phase-locked loop HG Ko, W Bae, GS Jeong, DK Jeong IEEE Access 7, 38035-38043, 2019 | 20 | 2019 |
| Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology W Bae, GS Jeong, Y Kim, HK Chi, DK Jeong IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2016 | 20 | 2016 |
| A mixed-signal risc-v signal analysis soc generator with a 16-nm finfet instance S Bailey, P Rigge, J Han, R Lin, EY Chang, H Mao, Z Wang, C Markley, ... IEEE Journal of Solid-State Circuits 54 (10), 2786-2801, 2019 | 19 | 2019 |
Deog-Kyoon JeongSeoul National University, Department of Electrical and Computer EngineeringVerified email at snu.ac.kr
