| Register transfer level information flow tracking for provably secure hardware design A Ardeshiricham, W Hu, J Marxen, R Kastner Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 171 | 2017 |
| Hardware information flow tracking W Hu, A Ardeshiricham, R Kastner ACM Computing Surveys (CSUR) 54 (4), 1-39, 2021 | 85 | 2021 |
| Property specific information flow analysis for hardware security verification W Hu, A Ardeshiricham, MS Gobulukoglu, X Wang, R Kastner 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 55 | 2018 |
| Clepsydra: Modeling timing flows in hardware designs A Ardeshiricham, W Hu, R Kastner 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 147-154, 2017 | 42 | 2017 |
| Towards property driven hardware security W Hu, A Althoff, A Ardeshiricham, R Kastner 2016 17th International Workshop on Microprocessor and SOC Test and …, 2016 | 36 | 2016 |
| Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans W Hu, L Zhang, A Ardeshiricham, J Blackstone, B Hou, Y Tai, R Kastner 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 707-713, 2017 | 35 | 2017 |
| VeriSketch: Synthesizing secure hardware designs with timing-sensitive information flow properties A Ardeshiricham, Y Takashima, S Gao, R Kastner Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications …, 2019 | 33 | 2019 |
| Imprecise security: quality and complexity tradeoffs for hardware information flow tracking W Hu, A Becker, A Ardeshiricham, Y Tai, P Ienne, D Mu, R Kastner 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 22 | 2016 |
| Examining the consequences of high-level synthesis optimizations on power side-channel L Zhang, W Hu, A Ardeshiricham, Y Tai, J Blackstone, D Mu, R Kastner 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 17 | 2018 |
| Identifying and measuring security critical path for uncovering circuit vulnerabilities W Hu, A Ardeshiricham, R Kastner 2017 18th International Workshop on Microprocessor and SOC Test and …, 2017 | 9 | 2017 |
| Techniques for improving security of circuitry designs based on a hardware description language R Kastner, A Ardeshiricham, W Hu US Patent 10,990,723, 2021 | 6 | 2021 |
| Verification and Synthesis of Information Flow Secure Hardware Designs A Ardeshiricham University of California, San Diego, 2020 | 5 | 2020 |
| A unified model for gate level propagation analysis J Blackstone, W Hu, A Althoff, A Ardeshiricham, L Zhang, R Kastner arXiv preprint arXiv:2012.02791, 2020 | 4 | 2020 |
| Integrating Information Flow Tracking into High-Level Synthesis Design Flow W Hu, A Ardeshiricham, L Wu, R Kastner Behavioral Synthesis for Hardware Security, 365-387, 2021 | 1 | 2021 |
Ryan KastnerProfessor of Computer Science and Engineering, UCSDVerified email at ucsd.edu
