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Jun Yin
Jun Yin
Associate Professor, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau
Email confirmado em um.edu.mo - Página inicial
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A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor
J Yin, J Yi, MK Law, Y Ling, MC Lee, KP Ng, B Gao, HC Luong, A Bermak, ...
IEEE Journal of Solid-State Circuits 45 (11), 2404-2420, 2010
2522010
A 57.5–90.1-GHz magnetically tuned multimode CMOS VCO
J Yin, HC Luong
IEEE Journal of solid-state circuits 48 (8), 1851-1861, 2013
1192013
A 21–48 GHz subharmonic injection-locked fractional-N frequency synthesizer for multiband point-to-point backhaul communications
A Li, S Zheng, J Yin, X Luo, HC Luong
IEEE Journal of Solid-State Circuits 49 (8), 1785-1799, 2014
842014
A 0.2-V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0-dBm output and 5.2-nW sleep power in 28-nm CMOS
S Yang, J Yin, H Yi, WH Yu, PI Mak, RP Martins
IEEE Journal of Solid-State Circuits 54 (5), 1351-1362, 2019
522019
A 0.18-V 382-W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS
H Yi, WH Yu, PI Mak, J Yin, RP Martins
IEEE Journal of Solid-State Circuits 53 (6), 1618-1627, 2018
462018
A 0.032-mm20.15-V Three-Stage Charge-Pump Scheme Using a Differential Bootstrapped Ring-VCO for Energy-Harvesting Applications
H Yi, J Yin, PI Mak, RP Martins
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (2), 146-150, 2017
412017
24.4 A 0.18 V 382µW bluetooth low-energy (BLE) receiver with 1.33 nW sleep power for energy-harvesting applications in 28nm CMOS
WH Yu, H Yi, PI Mak, J Yin, RP Martins
2017 IEEE international solid-state circuits conference (ISSCC), 414-415, 2017
392017
Ultra-low-power clock generation circuit for EPC standard UHF RDID transponders
F Song, J Yin, HL Liao, R Huang
Electronics Letters 44 (3), 199-201, 2008
352008
Low-phase-noise wideband mode-switching quad-core-coupled mm-wave VCO using a single-center-tapped switched inductor
Y Peng, J Yin, PI Mak, RP Martins
IEEE Journal of Solid-State Circuits 53 (11), 3232-3242, 2018
342018
An inverse-class-F CMOS oscillator with intrinsic-high-Q first harmonic and second harmonic resonances
CC Lim, H Ramiah, J Yin, PI Mak, RP Martins
IEEE Journal of Solid-State Circuits 53 (12), 3528-3539, 2018
282018
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm)
X Peng, J Yin, PI Mak, WH Yu, RP Martins
IEEE Journal of Solid-State Circuits 52 (6), 1495-1508, 2017
282017
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-CMOS Process
S Rong, J Yin, HC Luong
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (1), 109-113, 2015
272015
A Time-Interleaved Ring-VCO with Reduced 1/ Phase Noise Corner, Extended Tuning Range and Inherent Divided Output
J Yin, PI Mak, F Maloberti, RP Martins
IEEE Journal of Solid-State Circuits 51 (12), 2979-2991, 2016
262016
An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM
CC Lim, J Yin, PI Mak, H Ramiah, RP Martins
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 374-376, 2018
252018
Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications
R Martins, N Lourenco, N Horta, J Yin, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018
232018
A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs
S Yang, J Yin, PI Mak, RP Martins
IEEE Journal of Solid-State Circuits 54 (1), 88-98, 2018
212018
A 0.8 V 1.9 mW 53.7-to-72.0 GHz self-frequency-tracking injection-locked frequency divider
J Yin, HC Luong
2012 IEEE Radio Frequency Integrated Circuits Symposium, 305-308, 2012
212012
Transformer-based design techniques for oscillators and frequency dividers
HC Luong, J Yin
Springer International Publishing, 2016
202016
A 0.0056mm2all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrmsJitter and −249dB …
S Yang, J Yin, PI Mak, RP Martins
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 118-120, 2018
182018
A 0.07 mm 2.2 mW 10 GHz Current-Reuse Class-B/C Hybrid VCO Achieving 196-dBc/Hz FoM
MT Amin, J Yin, PI Mak, RP Martins
IEEE Microwave and Wireless Components Letters 25 (7), 457-459, 2015
172015
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