Robert Horst
Robert Horst
Adjunct Professor, University of Illinois
Verified email at illinois.edu
Title
Cited by
Cited by
Year
TNet: A reliable system area network
RW Horst
IEEE Micro 15 (1), 37-45, 1995
2251995
Active muscle assistance device and method
RW Horst
US Patent 6,966,882, 2005
2212005
Multiple-processor computer system with asynchronous execution of identical code streams
RW Horst
US Patent 5,317,726, 1994
1541994
Fail-fast, fail-functional, fault-tolerant multiprocessor system
RW Horst, WE Baker, RG Banton, JM Brown, WF Bruckert, WP Bunton, ...
US Patent 5,751,932, 1998
1481998
Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules
RW Cutts Jr, PC Norwood, KC Debacker, NA Mehta, DE Jewett, ...
US Patent 5,193,175, 1993
1481993
Self-checked, lock step processor pairs
RW Horst, DJ Garcia, WP Bunton, WF Bruckert, DL Fowler, CW Jones Jr, ...
US Patent 6,233,702, 2001
1452001
Multiple instruction issue in the NonStop Cyclone processor
RW Horst, RL Harris, RL Jardine
ACM SIGARCH Computer Architecture News 18 (2SI), 216-226, 1990
1431990
System and method for configuring adaptive sets of links between routers in a system area network (SAN)
RW Horst, WJ Watson, DA Brown, DJ Garcia, WP Bunton, DT Heron, ...
US Patent 6,950,428, 2005
1402005
Parallel pipelined merge engines
A Heirich, L Moll, M Shand, A Tam, R Horst
US Patent App. 10/864,609, 2004
1262004
Parallel pipelined merge engines
A Heirich, L Moll, M Shand, A Tam, RW Horst
US Patent 6,753,878, 2004
1262004
Memory system using linear array wafer scale integration architecture
RW Horst
US Patent 5,287,472, 1994
1251994
Active muscle assistance and resistance device and method
RW Horst
US Patent 7,537,573, 2009
1232009
ServerNet deadlock avoidance and fractahedral topologies
R Horst
Proceedings of International Conference on Parallel Processing, 274-280, 1996
1221996
Logical, fail-functional, dual central processor units formed from three processor units
RW Horst
US Patent 5,838,894, 1998
1171998
Network message routing using routing table information and supplemental enable information for deadlock prevention
JC Krause, DJ Garcia, RW Horst, GI Iswandhi, DP Sonnier, WJ Watson, ...
US Patent 5,914,953, 1999
1111999
Encoding for communicating data and commands
RW Horst, JC Krause
US Patent 5,867,501, 1999
1061999
Method of data communication flow control in a data processing system using busy/ready commands
RW Horst, WE Baker, LE Zalzala, WP Bunton, RW Cutts Jr, DJ Garcia, ...
US Patent 6,157,967, 2000
1042000
Multiple processor system with standby sparing
RW Horst, DJ Garcia
US Patent 6,496,940, 2002
1022002
Method and apparatus for synchronizing a plurality of processors
RW Horst
US Patent 5,384,906, 1995
931995
Refresh control for dynamic memory in multiple processor system
CE Peet Jr, JD Allison, KC Debacker, RW Horst
US Patent 5,146,589, 1992
861992
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