| Trace scheduling: A technique for global microcode compaction JA Fisher IEEE transactions on computers 30 (07), 478-490, 1981 | 1771 | 1981 |
| Very long instruction word architectures and the ELI-512 JA Fisher Proceedings of the 10th annual international symposium on Computer …, 1983 | 881 | 1983 |
| Instruction-level parallel processing: History, overview, and perspective BR Rau, JA Fisher The journal of Supercomputing 7, 9-50, 1993 | 592 | 1993 |
| Embedded computing: a VLIW approach to architecture, compilers and tools JA Fisher, P Faraboschi, C Young Elsevier, 2005 | 519 | 2005 |
| Lx: A technology platform for customizable VLIW embedded processing P Faraboschi, G Brown, JA Fisher, G Desoli, F Homewood Proceedings of the 27th annual international symposium on Computer …, 2000 | 471 | 2000 |
| Predicting conditional branch directions from previous runs of a program JA Fisher, SM Freudenberger ACM SIGPLAN Notices 27 (9), 85-95, 1992 | 331 | 1992 |
| Measuring the parallelism available for very long instruction word architectures Nicolau IEEE Transactions on Computers 100 (11), 968-976, 1984 | 264 | 1984 |
| Parallel processing: A smart compiler and a dumb machine JA Fisher, JR Ellis, JC Ruttenberg, A Nicolau Proceedings of the 1984 SIGPLAN symposium on Compiler construction, 37-47, 1984 | 218 | 1984 |
| The VLIW machine: A multiprocessor for compiling scientific code JA Fisher Computer 17 (07), 45-53, 1984 | 183 | 1984 |
| Deli: A new run-time control point G Desoli, N Mateev, E Duesterwald, P Faraboschi, JA Fisher 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 125 | 2002 |
| Custom-fit processors: Letting applications define architectures JA Fisher, P Faraboschi, G Desoli Proceedings of the 29th Annual IEEE/ACM International Symposium on …, 1996 | 125 | 1996 |
| The latest word in digital and media processing P Faraboschi, G Desoli, JA Fisher IEEE signal processing magazine 15 (2), 59-85, 1998 | 104 | 1998 |
| The optimization of horizontal microcode within and beyond basic blocks: An application of processor scheduling with resources JA Fisher New York University, 1979 | 103 | 1979 |
| Instruction scheduling for instruction level parallel processors P Faraboschi, JA Fisher, C Young Proceedings of the IEEE 89 (11), 1638-1659, 2001 | 88 | 2001 |
| Instruction-level parallel processing JA Fisher, R Rau Science 253 (5025), 1233-1241, 1991 | 81 | 1991 |
| System and method for isolating applications from each other JA Fisher, A Lain US Patent 7,051,340, 2006 | 79 | 2006 |
| Clustered instruction-level parallel processors P Faraboschi, G Desoli, JA Fisher Hewlett Packard Laboratories, 1999 | 77 | 1999 |
| System and method for facilitating profiling an application JA Fisher, G Desoli US Patent 7,194,732, 2007 | 76 | 2007 |
| Global code generation for instruction-level parallelism: Trace scheduling-2 JA Fisher Hewlett-Packard Laboratories, 1993 | 69 | 1993 |
| Customized instruction-sets for embedded processors JA Fisher Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 253-257, 1999 | 67 | 1999 |
