Andreas Steininger
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On the determination of dynamic errors for rise time measurement with an oscilloscope
C Mittermayer, A Steininger
IEEE Transactions on Instrumentation and Measurement 48 (6), 1103-1107, 1999
Testing and built-in self-test–A survey
A Steininger
Journal of Systems Architecture 46 (9), 721-747, 2000
Processor support for temporal predictability-the SPEAR design example
M Delvai, W Huber, P Puschner, A Steininger
15th Euromicro Conference on Real-Time Systems, 2003. Proceedings., 169-176, 2003
On the necessity of on-line-BIST in safety-critical applications-a case-study
A Steininger, C Scherrer
Digest of Papers. Twenty-Ninth Annual International Symposium on Fault …, 1999
Towards a systematic test for embedded automotive communication systems
E Armengaud, A Steininger, M Horauer
IEEE Transactions on Industrial Informatics 4 (3), 146-155, 2008
SAD-based stereo matching using FPGAs
K Ambrosch, M Humenberger, W Kubinger, A Steininger
Embedded Computer Vision, 121-138, 2009
Decentralised fault-tolerant clock pulse generation in VLSI chips
U Schmid, A Steininger
US Patent 7,791,394, 2010
Hardware implementation of an SAD based stereo vision algorithm
K Ambrosch, W Kubinger, M Humenberger, A Steininger
2007 IEEE Conference on Computer Vision and Pattern Recognition, 1-6, 2007
Pulse shape measurements by on-chip sense amplifiers of single event transients propagating through a 90 nm bulk CMOS inverter chain
M Hofbauer, K Schweiger, H Dietrich, H Zimmermann, KO Voss, B Merk, ...
IEEE Transactions on Nuclear Science 59 (6), 2778-2784, 2012
Built-in fault injection in hardware-the FIDYCO example
B Rahbaran, A Steininger, T Handl
Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic …, 2004
Investigations regarding process stability aspects in thread tapping Al-Si alloys
A Steininger, A Siller, F Bleicher
Procedia Engineering 100, 1124-1132, 2015
Is asynchronous logic more robust than synchronous logic?
B Rahbaran, A Steininger
IEEE Transactions on dependable and secure computing 6 (4), 282-294, 2008
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories
K Thaller, A Steininger
IEEE transactions on reliability 52 (4), 413-422, 2003
On the threat of metastability in an asynchronous fault-tolerant clock generation scheme
G Fuchs, M Függer, A Steininger
2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 127-136, 2009
Dealing with dormant faults in an embedded fault-tolerant computer system
C Scherrer, A Steininger
IEEE Transactions on Reliability 52 (4), 512-522, 2003
A prototype implementation of a ttp/c controller
H Kopetz, R Hexel, A Krüger, D Millinger, R Nossal, R Pallierer, ...
SAE Technical Paper, 1997
VLSI implementation of a fault-tolerant distributed clock generation
M Ferringer, G Fuchs, A Steininger, G Kempf
2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2006
Device and method for correcting errors in a processor having two execution units
W Harter, T Kottke, Y Collani, A Steininger, C Salloum
US Patent App. 11/293,385, 2006
Revision and verification of an enhanced UART
R Gallo, M Delvai, W Elmenreich, A Steininger
IEEE International Workshop on Factory Communication Systems, 2004 …, 2004
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip
D Dolev, M Függer, M Posch, U Schmid, A Steininger, C Lenzen
Journal of Computer and System Sciences 80 (4), 860-900, 2014
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