| Scalable high performance SDN switch architecture on FPGA for core networks S Wijeratne, A Ekanayake, S Jayaweera, D Ravishan, A Pasqual arXiv preprint arXiv:1910.13683, 2019 | 7 | 2019 |
| Virtual-link: A scalable multi-producer multi-consumer message queue architecture for cross-core communication Q Wu, J Beard, A Ekanayake, A Gerstlauer, LK John 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021 | 6 | 2021 |
| SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems Q Wu, A Ekanayake, R Li, J Beard, L John Proceedings of the 51st International Conference on Parallel Processing, 1-12, 2022 | 2 | 2022 |
| High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension R Senanayake, N Liyanage, S Wijeratne, S Atapattu, K Athukorala, ... 2017 IEEE 28th International Conference on Application-specific Systems …, 2017 | 1 | 2017 |
| SecurityCloak: Protection against cache timing and speculative memory access attacks F Mosquera, A Ekanayake, W Hua, K Kavi, G Mehta, L John Journal of Systems Architecture 150, 103107, 2024 | | 2024 |
Sasindu WijeratneUniversity of Southern CaliforniaVerified email at usc.edu
