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SUNIL PATHANIA
Title
Cited by
Cited by
Year
Predicting energy requirement for cooling the building using artificial neural network
R Kumar, RK Aggarwal, JD Sharma, S Pathania
Journal of Technology Innovations in Renewable Energy 1 (2), 113, 2012
282012
Thermal impact on high speed PCB interconnects
S Pathania, M Vasa, B Mutnury, R Sharma
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging …, 2019
92019
Analyzing crosstalk-induced effects in rough on-chip copper interconnects
S Pathania, S Kumar, R Sharma
IEEE Transactions on Components, Packaging and Manufacturing Technology 9 …, 2019
92019
Role of grain size on the effective resistivity of cu-graphene hybrid interconnects
R Kumar, S Pathania, S Guglani, A Kumar, S Kumar, S Roy, BK Kaushik, ...
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 1620-1625, 2020
82020
Crosstalk analysis for rough copper interconnects considering ternary logic
S Pathania, S Kumar, R Sharma
2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium …, 2018
62018
Image enhancement and iris recognition using SIFT feature extraction
H Kaur, S Pathania
Int. J. Adv. Res. Electron. Commun. Eng.(IJARECE) 5 (5), 1254-1256, 2016
42016
Multiphysics approach using computational fluid dynamics for signal integrity analysis in high speed serial links
S Pathania, M Vasa, A Shrivastava, S Kumar, V Kumar, S Muthusamy, ...
2019 Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3, 2019
32019
Speech Recognition using Hidden Markov Model and Viterbi Algorithm
S Bhardwaj, S Pathania, R Akela
International Journal of Advanced Research in Electronics and Communication …, 2015
32015
An artificial neural network surrogate model for repeater optimization in the presence of parametric uncertainty for hybrid copper-graphene interconnect networks
A Sharif, S Pathania, S Kushwaha, S Roy, R Sharma, BK Kaushik
2022 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2022
22022
Thermal sensitivity of dielectric materials in high-speed designs
S Pathania, B Mutnury, M Vasa, V Kumar, S Muthusamy, PK Seema, ...
2020 IEEE 29th Conference on Electrical Performance of Electronic Packaging …, 2020
22020
Investigating the role of sidewall surface roughness on the performance of through silicon vias
S Kumar, S Pathania, R Sharma
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), 1-4, 2017
22017
Design, analysis and selection of electric and magnetic loading for different rating of squirrel cage induction motors by using matlab gui software
D Sharma, RK Saini, S Pathania
Int. J. Innovative Res. Elec. Electron. Instrum. Control Eng 3 (4), 20-22, 2015
22015
Space Mapped Neuromodeling for Fast & Accurate Signal Integrity Analysis of Rough On-chip Copper Interconnects
S Kushwaha, S Guglani, N Soleimani, S Pathania, S Kumar, R Trinchero, ...
2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3, 2023
2023
Integrated thermal-electrical co-simulation
V Kumar, M Vasa, A Shrivastava, B Mutnury, PK Seema, S Muthusamy, ...
US Patent App. 17/716,527, 2023
2023
An Efficient Electrical-Thermal Co-Design Methodology for Analysis of High-Speed PCB Interconnects
S Pathania, S Kushwaha, S Kumar, M Vasa, A Shrivastava, V Kumar, ...
2023 IEEE MTT-S International Conference on Numerical Electromagnetic and …, 2023
2023
Signal integrity analysis of high speed onchip and chip-to-chip copper interconnects
S Pathania
2022
Crosstalk analysis for rough copper interconnects considering ternary logic
R Sharma, S Kumar, S Pathania
2020
Analyzing crosstalk-induced effects in rough on-chip copper interconnects
R Sharma, S Kumar, S Pathania
2019
Investigating the role of sidewall surface roughness on the performance of through silicon vias
R Sharma, S Kumar, S Pathania
2018
TRAFFIC JAM AND ACCIDENT DETECTION TECHNIQUES
R Shaili, S Pathania
2016
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Articles 1–20