Virtualized execution runtime for FPGA accelerators in the cloud M Asiatici, N George, K Vipin, SA Fahmy, P Ienne
Ieee Access 5, 1900-1910, 2017
90 2017 Through-glass vias for glass interposers and MEMS packaging applications fabricated using magnetic assembly of microscale metal wires MJ Laakso, SJ Bleiker, J Liljeholm, GE Mårtensson, M Asiatici, AC Fischer, ...
Ieee Access 6, 44306-44317, 2018
30 2018 Large-scale graph processing on FPGAs with caches for thousands of simultaneous misses M Asiatici, P Ienne
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
27 2021 Stop crying over your cache miss rate: Handling efficiently thousands of outstanding misses in FPGAs M Asiatici, P Ienne
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
25 2019 Through silicon vias with invar metal conductor for high-temperature applications M Asiatici, MJ Laakso, AC Fischer, G Stemme, F Niklaus
Journal of microelectromechanical systems 26 (1), 158-168, 2016
17 2016 Designing a virtual runtime for FPGA accelerators in the cloud M Asiatici, N George, K Vipin, SA Fahmy, P Ienne
2016 26th international conference on field programmable logic and …, 2016
17 2016 Dynaburst: Dynamically assemblying dram bursts over a multitude of random accesses M Asiatici, P Ienne
2019 29th International Conference on Field Programmable Logic and …, 2019
10 2019 In search of lost bandwidth: Extensive reordering of DRAM accesses on FPGA G Csordas, M Asiatici, P Ienne
2019 International Conference on Field-Programmable Technology (ICFPT), 188-196, 2019
8 2019 Request, coalesce, serve, and forget: Miss-optimized memory systems for bandwidth-bound cache-unfriendly applications on FPGAs M Asiatici, P Ienne
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (2), 1-33, 2021
5 2021 How many CPU cores is an FPGA worth? Lessons learned from accelerating string sorting on a CPU-FPGA system M Asiatici, D Maiorano, P Ienne
Journal of Signal Processing Systems 93, 1405-1417, 2021
5 2021 FPGAs in the datacenters: The case of parallel hybrid super scalar string sample sort M Asiatici, D Maiorano, P Ienne
2020 IEEE 31st International Conference on Application-specific Systems …, 2020
5 2020 Capacitive inertial sensing at high temperatures of up to 400° C M Asiatici, AC Fischer, H Rödjegård, S Haasl, G Stemme, F Niklaus
Sensors and Actuators A: Physical 238, 361-368, 2016
5 2016 Wide temperature range through silicon vias made of Invar and spin-on glass for interposers and MEMS MJ Laakso, M Asiatici, AC Fischer, G Stemme, F Niklaus
2016 IEEE 29th International Conference on Micro Electro Mechanical Systems …, 2016
4 2016 Snap-on user-space manager for dynamically reconfigurable system-on-chips A Guerrieri, S Kashani-Akhavan, M Asiatici, P Ienne
Ieee Access 7, 103938-103947, 2019
3 2019 Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities M Asiatici
EPFL, 2021
2021 Stop Crying Over Your Cache Miss Rate M Asiatici, P Ienne
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
2019 LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips A Guerrieri, S Kashani-Akhavan, M Asiatici, P Lombardi, B Belhadj, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
2018 FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5 ) M Asiatici, D Maiorano, P Ienne
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
2018 FPGAs in the Datacenters M Asiatici, D Maiorano, P Ienne
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
2018 FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS M Asiatici, D Maiorano, P Ienne
2018 
Paolo IenneProfessor, EPFLEmail confirmado em epfl.ch
