| PMCTrack: Delivering performance monitoring counter support to the OS scheduler JC Saez, A Pousa, R Rodriíguez-Rodriíguez, F Castro, M Prieto-Matias The Computer Journal 60 (1), 60-85, 2017 | 46 | 2017 |
| Reducing writes in phase-change memory environments by using efficient cache replacement policies R Rodriguez-Rodriguez, F Castro, D Chaver, L Pinuel, F Tirado 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 93-96, 2013 | 35 | 2013 |
| Towards completely fair scheduling on asymmetric single-ISA multicore processors JC Saez, A Pousa, F Castro, D Chaver, M Prieto-Matias Journal of Parallel and Distributed Computing 102, 115-131, 2017 | 34 | 2017 |
| ACFS: A completely fair scheduler for asymmetric single-ISA multicore systems JC Saez, A Pousa, F Castro, D Chaver, M Prieto-Matias Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2027-2032, 2015 | 30 | 2015 |
| DMDC: delayed memory dependence checking through age-based filtering F Castro, L Pinuel, D Chaver, M Prieto, M Huang, F Tirado 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006 | 22 | 2006 |
| LFOC: A lightweight fairness-oriented cache clustering policy for commodity multicores A Garcia-Garcia, JC Saez, F Castro, M Prieto-Matias Proceedings of the 48th international conference on parallel processing, 1-10, 2019 | 18 | 2019 |
| L1 data cache power reduction using a forwarding predictor P Carazo, R Apolloni, F Castro, D Chaver, L Pinuel, F Tirado Integrated Circuit and System Design. Power and Timing Modeling …, 2011 | 17 | 2011 |
| Load-store queue management: an energy-efficient design based on a state-filtering mechanism F Castro, D Chaver, L Pinuel, M Prieto, F Tirado, M Huang 2005 International Conference on Computer Design, 617-624, 2005 | 17 | 2005 |
| An OS-oriented performance monitoring tool for multicore systems JC Saez, J Casas, A Serrano, R Rodríguez-Rodríguez, F Castro, ... Euro-Par 2015: Parallel Processing Workshops: Euro-Par 2015 International …, 2015 | 16 | 2015 |
| Stack filter: Reducing L1 data cache power consumption R González-Alberquilla, F Castro, L Pinuel, F Tirado Journal of Systems Architecture 56 (12), 685-695, 2010 | 13 | 2010 |
| Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors JC Saez, F Castro, M Prieto-Matias Proceedings of the 49th International Conference on Parallel Processing, 1-11, 2020 | 12 | 2020 |
| Substituting associative load queue with simple hash tables in out-of-order microprocessors A Garg, F Castro, M Huang, D Chaver, L Pinuel, M Prieto Proceedings of the 2006 international symposium on Low power electronics and …, 2006 | 12 | 2006 |
| Write-aware replacement policies for pcm-based systems R Rodríguez-Rodríguez, F Castro, D Chaver, R González-Alberquilla, ... The Computer Journal 58 (9), 2000-2025, 2015 | 11 | 2015 |
| Reuse detector: Improving the management of STT-RAM SLLCs R Rodríguez-Rodríguez, J Díaz, F Castro, P Ibáñez, D Chaver, V Viñals, ... The Computer Journal 61 (6), 856-880, 2018 | 9 | 2018 |
| Exploring the throughput-fairness trade-off on asymmetric multicore systems JC Saez, A Pousa, F Castro, D Chaver, M Prieto-Matías Euro-Par 2014: Parallel Processing Workshops: Euro-Par 2014 International …, 2014 | 9 | 2014 |
| Delivering fairness and priority enforcement on asymmetric multicore systems via OS scheduling JC Saez, F Castro, D Chaver, M Prieto ACM SIGMETRICS Performance Evaluation Review 41 (1), 343-344, 2013 | 9 | 2013 |
| Memory disambiguation hardware: a review F Castro, D Chaver, L Piñuel, M Prieto, F Tirado Fernández Journal of Computer Science & Technology 8, 2008 | 9 | 2008 |
| LFOC+: A fair OS-level cache-clustering policy for commodity multicore systems JC Saez, F Castro, G Fanizzi, M Prieto-Matias IEEE Transactions on Computers 71 (8), 1952-1967, 2021 | 8 | 2021 |
| Stack oriented data cache filtering R González-Alberquilla, F Castro, L Piñuel, F Tirado Proceedings of the 7th IEEE/ACM international conference on Hardware …, 2009 | 7 | 2009 |
| A power-efficient and scalable load-store queue design F Castro, D Chaver, L Pinuel, M Prieto, MC Huang, F Tirado Integrated Circuit and System Design. Power and Timing Modeling …, 2005 | 7 | 2005 |
Daniel ChaverAssociate Professor, Universidad Complutense de MadridEmail confirmado em ucm.es
