| Chipnemo: Domain-adapted llms for chip design M Liu, TD Ene, R Kirby, C Cheng, N Pinckney, R Liang, J Alben, H Anand, ... arXiv preprint arXiv:2311.00176, 2023 | 124 | 2023 |
| Analysis of the impact of process variations and manufacturing defects on the performance of carbon-nanotube FETs S Banerjee, A Chaudhuri, K Chakrabarty IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 38 | 2020 |
| Analysis of process variations, defects, and design-induced coupling in memristors A Chaudhuri, K Chakrabarty 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 38 | 2018 |
| C-testing and efficient fault localization for AI accelerators A Chaudhuri, C Liu, X Fan, K Chakrabarty IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 22 | 2021 |
| Functional criticality classification of structural faults in AI accelerators A Chaudhuri, J Talukdar, F Su, K Chakrabarty 2020 IEEE International Test Conference (ITC), 1-5, 2020 | 22 | 2020 |
| Efficient fault-criticality analysis for AI accelerators using a neural twin A Chaudhuri, CY Chen, J Talukdar, S Madala, AK Dubey, K Chakrabarty 2021 IEEE International Test Conference (ITC), 73-82, 2021 | 21 | 2021 |
| Built-in self-test for inter-layer vias in monolithic 3D ICs A Chaudhuri, S Banerjee, H Park, BW Ku, K Chakrabarty, SK Lim 2019 IEEE European Test Symposium (ETS), 1-6, 2019 | 18 | 2019 |
| Functional Criticality Analysis of Structural Faults in AI Accelerators A Chaudhuri, J Talukdar, F Su, K Chakrabarty IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 14 | 2022 |
| C-Testing of AI Accelerators * A Chaudhuri, C Liu, X Fan, K Chakrabarty 2020 IEEE 29th Asian Test Symposium (ATS), 1-6, 2020 | 14 | 2020 |
| Fault-criticality assessment for AI accelerators using graph convolutional networks A Chaudhuri, J Talukdar, J Jung, GJ Nam, K Chakrabarty 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 13 | 2021 |
| Fault-tolerant neuromorphic computing systems A Chaudhuri, M Liu, K Chakrabarty 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 13 | 2019 |
| RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 11 | 2019 |
| Variation-aware delay fault testing for carbon-nanotube FET circuits S Banerjee, A Chaudhuri, A Ning, K Chakrabarty IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (2), 409-422, 2021 | 10 | 2021 |
| Hardware fault tolerance for binary RRAM crossbars A Chaudhuri, B Yan, Y Chen, K Chakrabarty 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 10 | 2019 |
| Single chip self-tunable N-input N-output PID control system with integrated analog front-end for miniature robotics AS Bhandari, A Chaudhuri, S Roy, S Negi, M Sharad 2017 IEEE 14th International Conference on Networking, Sensing and Control …, 2017 | 10 | 2017 |
| Design automation and test solutions for monolithic 3D ICs L Zhu, A Chaudhuri, S Banerjee, G Murali, P Vanna-Iampikul, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-49, 2021 | 9 | 2021 |
| RTL-to-GDS design tools for monolithic 3D ICs J Kim, G Murali, P Vanna-Iampikul, E Lee, D Kim, A Chaudhuri, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 9 | 2020 |
| Advances in design and test of monolithic 3-D ICs A Chaudhuri, S Banerjee, H Park, J Kim, G Murali, E Lee, D Kim, SK Lim, ... IEEE Design & Test 37 (4), 92-100, 2020 | 9 | 2020 |
| Built-in self-test of high-density and realistic ILV layouts in monolithic 3-D ICs A Chaudhuri, S Banerjee, J Kim, SK Lim, K Chakrabarty IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (3), 296-309, 2023 | 8 | 2023 |
| Special session: Fault criticality assessment in ai accelerators A Chaudhuri, J Talukdar, K Chakrabarty 2022 IEEE 40th VLSI Test Symposium (VTS), 1-4, 2022 | 7 | 2022 |
Krishnendu ChakrabartyFulton Professor of Microelectronics, School of Electrical and Computer and Energy EngineeringVerified email at asu.edu
