| Buffer insertion for noise and delay optimization CJ Alpert, A Devgan, ST Quay IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1999 | 295 | 1999 |
| Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation CJ Alpert, A Devgan, ST Quay US Patent 6,347,393, 2002 | 191 | 2002 |
| Optimum buffer placement for noise avoidance CJ Alpert, ST Quay, A Devgan US Patent 6,117,182, 2000 | 191 | 2000 |
| Buffer insertion with accurate gate and interconnect delay computation CJ Alpert, A Devgan, ST Quay Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 479-484, 1999 | 150 | 1999 |
| Porosity aware buffered steiner tree construction CJ Alpert, RG Gandham, J Hu, ST Quay US Patent 7,065,730, 2006 | 114 | 2006 |
| Method and system for re-routing interconnects within an integrated circuit design having blockages and bays CJ Alpert, RG Gandham, J Hu, JL Neves, ST Quay US Patent 6,401,234, 2002 | 97 | 2002 |
| Buffered Steiner trees for difficult instances CJ Alpert, M Hrkić, J Hu, AB Kahng, J Lillis, B Liu, ST Quay, ... Proceedings of the 2001 international symposium on Physical design, 4-9, 2001 | 90 | 2001 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 83 | 2007 |
| Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management CJ Alpert, RG Gandham, M Hrkic, ST Quay US Patent 7,127,696, 2006 | 54 | 2006 |
| Interconnect synthesis without wire tapering CJ Alpert, A Devgan, JP Fishburn, ST Quay IEEE Transactions on computer-aided design of integrated circuits and …, 2001 | 51 | 2001 |
| Fast interconnect synthesis with layer assignment Z Li, CJ Alpert, S Hu, T Muhmud, ST Quay, PG Villarrubia Proceedings of the 2008 international symposium on Physical design, 71-77, 2008 | 47 | 2008 |
| Buffer insertion with adaptive blockage avoidance J Hu, CJ Alpert, ST Quay, G Gandham Proceedings of the 2002 international symposium on Physical design, 92-97, 2002 | 47 | 2002 |
| Steiner tree optimization for buffers, blockages, and bays CJ Alpert, G Gandham, J Hu, JI Neves, ST Quay, SS Sapatnekar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 45 | 2001 |
| Probabilistic congestion prediction with partial blockages CJ Alpert, Z Li, ST Quay US Patent 7,299,442, 2007 | 40 | 2007 |
| Probabilistic congestion prediction with partial blockages C Alpert, Z Li, S Quay US Patent App. 11/032,878, 2006 | 40 | 2006 |
| Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique C Alpert, C Chu, G Gandham, M Hrkic, J Hu, C Kashyap, S Quay IEEE Transactions on computer-aided design of integrated circuits and …, 2004 | 35 | 2004 |
| Buffer library selection CJ Alpert, RG Gandham, JL Neves, ST Quay Proceedings 2000 International Conference on Computer Design, 221-226, 2000 | 34 | 2000 |
| Fast and flexible buffer trees that navigate the physical layout environment CJ Alpert, M Hrkić, J Hu, ST Quay Proceedings of the 41st annual Design Automation Conference, 24-29, 2004 | 30 | 2004 |
| Porosity-aware buffered Steiner tree construction CJ Alpert, G Gandham, M Hrkic, J Hu, ST Quay, CN Sze IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 30 | 2004 |
| Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms CI Gabele, ST Quay, PG Villarrubia, PT Patel, JP Watson US Patent 6,360,350, 2002 | 30 | 2002 |
