Mário Véstias
Mário Véstias
INESC-ID/ISEL/IPL
Email confirmado em deetc.isel.ipl.pt
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Trends of CPU, GPU and FPGA for high-performance computing
M Vestias, H Neto
2014 24th International Conference on Field Programmable Logic and …, 2014
492014
Decimal multiplier on FPGA using embedded binary multipliers
HC Neto, MP Véstias
2008 International Conference on Field Programmable Logic and Applications …, 2008
352008
Parallel decimal multipliers using binary multipliers
MP Véstias, HC Neto
2010 VI Southern Programmable Logic Conference (SPL), 73-78, 2010
342010
Architectures and compilers to support reconfigurable computing
JMP Cardoso, MP Vestístias
XRDS: Crossroads, The ACM Magazine for Students 5 (3), 15-22, 1999
321999
Double-precision gauss-jordan algorithm with partial pivoting on fpgas
R Duarte, H Neto, M Véstias
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
222009
Area and performance optimization of a generic network-on-chip architecture
MP Véstias, HC Neto
Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006
222006
Multi-core for K-means clustering on FPGA
J Canilho, M Véstias, H Neto
2016 26th International Conference on Field Programmable Logic and …, 2016
202016
Co-synthesis of a configurable SoC platform based on a network on chip architecture
MP Véstias, HC Neto
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
202006
Iterative decimal multiplication using binary arithmetic
MP Véstias, HC Neto
2011 VII Southern Conference on Programmable Logic (SPL), 257-262, 2011
152011
Parallel dot-products for deep learning on FPGA
M Véstias, RP Duarte, JT de Sousa, H Neto
2017 27th International Conference on Field Programmable Logic and …, 2017
14*2017
Design of high-speed Viterbi decoders on Virtex-6 FPGAs
M Véstias, H Neto, H Sarmento
2012 15th Euromicro Conference on Digital System Design, 938-945, 2012
132012
Router design for application specific Networks-on-Chip on reconfigurable systems
MP Vestias, HC Neto
2007 International Conference on Field Programmable Logic and Applications …, 2007
132007
Revisiting the Newton-Raphson Iterative Method for Decimal Division.
MP Vestias, HC Neto
FPL, 138-143, 2011
122011
Lite-CNN: a high-performance architecture to execute CNNs in low density FPGAs
M Véstias, RP Duarte, JT de Sousa, HC Neto
2018 28th International Conference on Field Programmable Logic and …, 2018
112018
Redes CISCO para profissionais
V Mário
Lisboa: FCA–Editora, 2009
11*2009
A generic network-on-chip architecture for reconfigurable systems: Implementation and evaluation
MP Vestias, HC Neto
2006 International Conference on Field Programmable Logic and Applications, 1-4, 2006
102006
Parallel decimal multipliers and squarers using Karatsuba-Ofman's algorithm
M Vestias, H Neto
2012 15th Euromicro Conference on Digital System Design, 782-788, 2012
92012
High-performance reconfigurable computing granularity
MP Véstias
Encyclopedia of Information Science and Technology, Third Edition, 3558-3567, 2015
82015
Efficient implementation of a single-precision floating-point arithmetic unit on FPGA
W José, AR Silva, H Neto, M Véstias
2014 24th International Conference on Field Programmable Logic and …, 2014
82014
Analysis of matrix multiplication on high density Virtex-7 FPGA
W José, AR Silva, H Neto, M Véstias
2013 23rd International Conference on Field programmable Logic and …, 2013
82013
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