Joel Emer

Citado por

	Todos	Desde 2016
Citações	19205	9540
Índice h	60	39
Índice i10	133	90

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Coautores

Aamer JaleelArchitecture Research Group (ARG), Nvidia ResearchEmail confirmado em nvidia.com
Vivienne SzeAssociate Professor, EECS at MITEmail confirmado em mit.edu
Michael C. AdlerIntelEmail confirmado em intel.com
Yu-Hsin ChenResearch Scientist, FacebookEmail confirmado em fb.com
Steven K. ReinhardtMicrosoftEmail confirmado em microsoft.com
Angshuman ParasharSr. Research Scientist, NVIDIAEmail confirmado em nvidia.com
Steve KecklerVice President of Architecture Research, NVIDIAEmail confirmado em cs.utexas.edu
Dean TullsenProfessor of Computer Science and Engineering, UC San DiegoEmail confirmado em eng.ucsd.edu
William HasenplaughD. E. Shaw ResearchEmail confirmado em mit.edu
Susan J EggersProfessor of Computer Science, University of WashingtonEmail confirmado em cs.washington.edu
Henry M. LevyProfessor and Wissner-Slivka Chair, Paul G. Allen School of Computer Science & EngineeringEmail confirmado em cs.washington.edu
Tien-Ju YangMassachusetts Institute of TechnologyEmail confirmado em mit.edu
William DallyBell Professor of Engineering, Stanford University; Chief Scientist, NVIDIAEmail confirmado em stanford.edu
Rangharajan VenkatesanSenior Research Scientist, NVIDIAEmail confirmado em nvidia.com
Kermin Elliott FlemingIntel CorporationEmail confirmado em intel.com
Brucek KhailanyDirector of VLSI Research, NVIDIAEmail confirmado em cva.stanford.edu
Todd AustinProfessor of Computer Science and Electrical Engineering, University of MichiganEmail confirmado em umich.edu
Tushar KrishnaAssistant Professor, Georgia TechEmail confirmado em ece.gatech.edu
Yakun Sophia ShaoAssistant Professor, UC BerkeleyEmail confirmado em berkeley.edu
Neal CragoSenior Research Scientist, Nvidia ResearchEmail confirmado em nvidia.com

Joel Emer

Professor of the Practice, MIT - Sr. Distinguished Research Scientist, Nvidia

Email confirmado em csail.mit.edu - Página inicial

Computer Architecture


Título Ordenar por citações Ordenar por ano Ordenar por título	Citado por Citado por	Ano
Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016	1678	2016
Efficient processing of deep neural networks: A tutorial and survey V Sze, YH Chen, TJ Yang, JS Emer Proceedings of the IEEE 105 (12), 2295-2329, 2017	1393	2017
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm Proceedings of the 23rd annual international symposium on Computer …, 1996	1148	1996
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003	1113	2003
Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks YH Chen, J Emer, V Sze ACM SIGARCH Computer Architecture News 44 (3), 367-379, 2016	874	2016
Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007	816	2007
High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH Computer Architecture News 38 (3), 60-71, 2010	726	2010
Simultaneous multithreading: A platform for next-generation processors SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen IEEE micro 17 (5), 12-19, 1997	648	1997
Scnn: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017	571	2017
The soft error problem: An architectural perspective SS Mukherjee, J Emer, SK Reinhardt 11th International Symposium on High-Performance Computer Architecture, 243-247, 2005	512	2005
Memory dependence prediction using store sets GZ Chrysos, JS Emer ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998	427	1998
Adaptive insertion policies for managing shared caches A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer Proceedings of the 17th international conference on Parallel architectures …, 2008	388	2008
Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer 2012 39th Annual International Symposium on Computer Architecture (ISCA …, 2012	382	2012
Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading JL Lo, JS Emer, HM Levy, RL Stamm, DM Tullsen, SJ Eggers ACM Transactions on Computer Systems (TOCS) 15 (3), 322-354, 1997	367	1997
Techniques to reduce the soft error rate of a high-performance microprocessor C Weaver, J Emer, SS Mukherjee, SK Reinhardt ACM SIGARCH Computer Architecture News 32 (2), 264, 2004	354	2004
Asim: A performance model framework J Emer, P Ahuja, E Borch, A Klauser, CK Luk, S Manne, SS Mukherjee, ... Computer 35 (2), 68-76, 2002	304	2002
Predictive sequential associative cache B Calder, D Grunwald, J Emer Proceedings. Second International Symposium on High-Performance Computer …, 1996	283	1996
Computing architectural vulnerability factors for address-based structures A Biswas, P Racunas, R Cheveresan, J Emer, SS Mukherjee, R Rangan 32nd International Symposium on Computer Architecture (ISCA'05), 532-543, 2005	272	2005
SHiP: Signature-based hit predictor for high performance caching CJ Wu, A Jaleel, W Hasenplaugh, M Martonosi, SC Steely Jr, J Emer Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011	249	2011
Loose loops sink chips E Borch, E Tune, S Manne, J Emer Proceedings Eighth International Symposium on High Performance Computer …, 2002	217	2002

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