Ryan Kastner
Ryan Kastner
Professor of Computer Science and Engineering, UCSD
Verified email at - Homepage
Cited by
Cited by
Fast template placement for reconfigurable computing systems
K Bazargan, R Kastner, M Sarrafzadeh
IEEE design & Test of Computers 17 (1), 68-83, 2000
Instruction generation for hybrid reconfigurable systems
R Kastner, A Kaplan, SO Memik, E Bozorgzadeh
ACM Transactions on Design Automation of Electronic Systems (TODAES) 7 (4 …, 2002
RIFFA 2.1: A reusable integration framework for FPGA accelerators
M Jacobsen, D Richmond, M Hogains, R Kastner
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (4), 1-23, 2015
Fpga-based face detection system using haar classifiers
J Cho, S Mirzaei, J Oberg, R Kastner
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2009
Design of a low-cost, underwater acoustic modem for short-range sensor networks
B Benson, Y Li, R Kastner, B Faunce, K Domond, D Kimball, C Schurgers
OCEANS'10 IEEE SYDNEY, 1-9, 2010
SurfNoC: A low latency and provably non-interfering approach to secure networks-on-chip
HMG Wassel, Y Gao, JK Oberg, T Huffmire, R Kastner, FT Chong, ...
ACM SIGARCH Computer Architecture News 41 (3), 583-594, 2013
Sapper: A language for hardware-level security policy enforcement
X Li, V Kashyap, JK Oberg, M Tiwari, VR Rajarathinam, R Kastner, ...
Proceedings of the 19th international conference on Architectural support …, 2014
A swarm of autonomous miniature underwater robot drifters for exploring submesoscale ocean dynamics
JS Jaffe, PJS Franks, PLD Roberts, D Mirza, C Schurgers, R Kastner, ...
Nature communications 8 (1), 1-8, 2017
Predictable routing
R Kastner, E Bozorgzadeh, M Sarrafzadeh
IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000
Accelerating Viola-Jones face detection to FPGA-level using GPUs
D Hefenbrock, J Oberg, NTN Thanh, R Kastner, SB Baden
2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010
Register transfer level information flow tracking for provably secure hardware design
A Ardeshiricham, W Hu, J Marxen, R Kastner
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems
T Huffmire, B Brotherton, G Wang, T Sherwood, R Kastner, T Levin, ...
2007 IEEE Symposium on Security and Privacy (SP'07), 281-295, 2007
FPGA implementation of high speed FIR filters using add and shift method
S Mirzaei, A Hosangadi, R Kastner
2006 International Conference on Computer Design, 308-313, 2006
Pattern routing: Use and theory for increasing predictability and avoiding coupling
R Kastner, E Bozorgzadeh, M Sarrafzadeh
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security
M Tiwari, JK Oberg, X Li, J Valamehr, T Levin, B Hardekopf, R Kastner, ...
ACM SIGARCH Computer Architecture News 39 (3), 189-200, 2011
Instruction generation and regularity extraction for reconfigurable processors
P Brisk, A Kaplan, R Kastner, M Sarrafzadeh
Proceedings of the 2002 international conference on Compilers, architecture …, 2002
Congestion estimation during top-down placement
X Yang, R Kastner, M Sarrafzadeh
Proceedings of the 2001 international symposium on Physical design, 164-169, 2001
An overview of hardware security and trust: Threats, countermeasures, and design tools
W Hu, CH Chang, A Sengupta, S Bhunia, R Kastner, H Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
Detecting hardware trojans with gate-level information-flow tracking
W Hu, B Mao, J Oberg, R Kastner
Computer 49 (8), 44-52, 2016
Parallel programming for FPGAs
R Kastner, J Matai, S Neuendorffer
arXiv preprint arXiv:1805.03648, 2018
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