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Hari Mohan Gaur, Ph.D
Hari Mohan Gaur, Ph.D
Goethe-Uni Frankfurt (Campus Riedberg), Germany
Verified email at ieee.org
Title
Cited by
Cited by
Year
In-depth comparative analysis of reversible gates for designing logic circuits
HM Gaur, AK Singh, U Ghanekar
Procedia Computer Science 125, 810-817, 2018
402018
Design of reversible circuits with high testability
HM Gaur, AK Singh
Electronics Letters 52 (13), 1102-1104, 2016
362016
A review on online testability for reversible logic
HM Gaur, AK Singh, U Ghanekar
Procedia Computer Science 70, 384-391, 2015
322015
Testable design of reversible circuits using parity preserving gates
HM Gaur, AK Singh, U Ghanekar
IEEE Design & Test 35 (4), 56-64, 2017
242017
A new DFT methodology for k-CNOT reversible circuits and its implementation using quantum-dot cellular automata
HM Gaur, AK Singh, U Ghanekar
Optik 127 (22), 10593-10601, 2016
192016
Offline testing of reversible logic circuits: an analysis
HM Gaur, AK Singh, U Ghanekar
Integration 62, 50-67, 2018
172018
Design of reversible arithmetic logic unit with built-in testability
HM Gaur, AK Singh, U Ghanekar
IEEE Design & Test 36 (5), 54-61, 2019
162019
A Comprehensive and Comparative Study on Online Testability for Reversible Logic
HM Gaur, AK Singh, U Ghanekar
162016
Computational analysis and comparison of reversible gates for design and test of logic circuits
HM Gaur, AK Singh, A Mohan, DK Pradhan
International Journal of Electronics 106 (11), 1679-1693, 2019
132019
Reversible logic: An introduction
HM Gaur, TN Sasamal, AK Singh, A Mohan, DK Pradhan
Design and Testing of Reversible Logic, 3-18, 2020
112020
Design for stuck-at fault testability in Toffoli–Fredkin reversible circuits
HM Gaur, AK Singh, U Ghanekar
National Academy Science Letters 44 (3), 215-220, 2021
92021
Design for Stuck-at Fault Testability in MCT based Reversible Circuits
UG HM Gaur, AK Singh
Defence Science Journal 68 (4), 381-387, 2018
9*2018
Area and energy optimized multilayer QCA-based 4N-bit scalable multiplier (M4N-MUL)
V Jain, DK Sharma, HM Gaur
The European Physical Journal Plus 137 (11), 1281, 2022
82022
An efficient design of scalable reversible multiplier with testability
HM Gaur, AK Singh, U Ghanekar
Journal of Circuits, Systems and Computers 31 (10), 2250179, 2022
82022
Fault detection in multiple controlled Fredkin circuits
AK Singh, HM Gaur, U Ghanekar
IET Circuits, Devices & Systems 13 (5), 723-729, 2019
82019
Reversible circuits with testability using quantum controlled NOT and swap gates
HM Gaur, AK Singh, U Gaur
Indian Journal of Pure & Applied Physics (IJPAP) 56 (7), 529-532, 2018
82018
Design of single-bit fault-tolerant reversible circuits
HM Gaur, AK Singh, A Mohan, M Fujita, DK Pradhan
IEEE Design & Test 38 (2), 89-96, 2020
72020
Fault models and test approaches in reversible logic circuits
HM Gaur, TN Sasamal, AK Singh, A Mohan
Design and testing of reversible logic, 153-167, 2020
72020
Novel approaches for designing reversible counters
TN Sasamal, HM Gaur, AK Singh, A Mohan
Design and testing of reversible logic, 37-48, 2020
72020
Simplification and modification of multiple controlled Toffoli circuits for testability
HM Gaur, AK Singh, U Ghanekar
Journal of Computational Electronics 18, 356-363, 2019
72019
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