Antonio Toro Frias
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Reliability simulation for analog ICs: Goals, solutions, and challenges
A Toro-Frias, P Martin-Lloret, J Martín-Martínez, R Castro-López, E Roca, ...
Integration 55, 341-348, 2016
252016
CASE: A reliability simulation tool for analog ICs
P Martin-Lloret, A Toro-Frías, R Castro-López, E Roca, FV Fernández, ...
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
102017
An automated layout-aware design flow
A Toro-Frias, R Castro-Lopez, E Roca, FV Fernández
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
92012
A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs
P Martín-Lloret, A Toro-Frías, J Martín-Martínez, R Castro-López, E Roca, ...
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
72017
Including a stochastic model of aging in a reliability simulation flow
A Toro-Frias, P Martin-Lloret, R Castro-López, E Roca, FV Fernández, ...
2017 14th International Conference on Synthesis, Modeling, Analysis and …, 2017
62017
A model parameter extraction methodology including time-dependent variability for circuit reliability simulation
J Diaz-Fortuny, P Saraza-Canflanca, A Toro-Frias, R Castro-López, ...
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
42018
A fast and accurate reliability simulation method for analog circuits
A Toro-Frias, R Castro-López, E Roca, FV Fernández, J Martin-Martinez, ...
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
42015
Lifetime calculation using a stochastic reliability simulator for analog ICs
A Toro-Frias, P Martin-Lloret, J Martinez, R Castro-López, E Roca, ...
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
32018
Design considerations of an SRAM array for the statistical validation of time-dependent variability models
P Saraza-Canflanca, D Malagon, F Passos, A Toro, J Nuñez, ...
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
22018
Automated massive RTN characterization using a transistor array chip
P Saraza, J Diaz-Fortuny, A Toro-Frias, R Castro-López, E Roca, ...
2018 15th International Conference on Synthesis, Modeling, Analysis and …, 2018
22018
Layout-aware pareto fronts of electronic circuits
A Toro-Frias, R Castro-López, E Roca, FV Fernández
2011 20th European Conference on Circuit Theory and Design (ECCTD), 345-348, 2011
22011
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator
A Toro-Frias, P Saraza-Canflanca, F Passos, P Martin-Lloret, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 78-83, 2019
12019
Circuit reliability prediction: challenges and solutions for the device time-dependent variability characterization roadblock
M Nafria, J Diaz-Fortuny, P Saraza-Canflanca, J Martin-Martinez, E Roca, ...
2021 IEEE Latin America Electron Devices Conference (LAEDC), 1-4, 2021
2021
Modeling of variability and reliability in analog circuits
J Martin-Martinez, J Diaz-Fortuny, A Toro-Frias, P Martin-Lloret, ...
Modelling Methodologies in Analogue Integrated Circuit Design, 179, 2020
2020
Diseño de circuitos analógicos y de señal mixta con consideraciones de diseño fisico y variabilidad
A Toro Frías
2017
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