| Roofline: an insightful visual performance model for multicore architectures S Williams, A Waterman, D Patterson Communications of the ACM 52 (4), 65-76, 2009 | 2817 | 2009 |
| Single-chip microprocessor that communicates directly using light C Sun, MT Wade, Y Lee, JS Orcutt, L Alloatti, MS Georgas, AS Waterman, ... Nature 528 (7583), 534-538, 2015 | 1261 | 2015 |
| Chisel: constructing hardware in a scala embedded language J Bachrach, H Vo, B Richards, Y Lee, A Waterman, R Avižienis, ... Proceedings of the 49th Annual Design Automation Conference, 1216-1225, 2012 | 1111 | 2012 |
| The risc-v instruction set manual, volume i: User-level isa A Waterman, Y Lee, DA Patterson, K Asanovic CS Division, EECE Department, University of California, Berkeley, 28, 2014 | 799* | 2014 |
| The rocket chip generator K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS …, 2016 | 713 | 2016 |
| The risc-v instruction set manual, volume i: Base user-level isa A Waterman, Y Lee, DA Patterson, K Asanovic EECS Department, UC Berkeley, Tech. Rep. UCB/EECS-2011-62 116, 1-32, 2011 | 227 | 2011 |
| Design of the RISC-V instruction set architecture AS Waterman University of California, Berkeley, 2016 | 217 | 2016 |
| RAMP gold: an FPGA-based architecture simulator for multiprocessors Z Tan, A Waterman, R Avizienis, Y Lee, H Cook, D Patterson, K Asanović Proceedings of the 47th Design Automation Conference, 463-468, 2010 | 174 | 2010 |
| The risc-v instruction set manual volume i: Unprivileged isa A Waterman, K Asanovic Document Version 20191213, 1-4, 2019 | 173 | 2019 |
| A 45nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators Y Lee, A Waterman, R Avizienis, H Cook, C Sun, V Stojanović, K Asanović ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 199-202, 2014 | 169 | 2014 |
| The RISC-V instruction set manual, volume II: Privileged architecture A Waterman, K Asanovic RISC-V Foundation, 1-4, 2019 | 156 | 2019 |
| An agile approach to building RISC-V microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... ieee Micro 36 (2), 8-20, 2016 | 147 | 2016 |
| The RISC-V instruction set manual volume II: Privileged architecture version 1.7 A Waterman, Y Lee, R Avizienis, DA Patterson, K Asanovic EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2015-49, 2015 | 121 | 2015 |
| The rocket chip generator. EECS Department K Asanovic, R Avizienis, J Bachrach, S Beamer, D Biancolin, C Celio, ... University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17 4, 2016 | 119 | 2016 |
| A case for FAME: FPGA architecture model execution Z Tan, A Waterman, H Cook, S Bird, K Asanović, D Patterson Proceedings of the 37th annual international symposium on Computer …, 2010 | 113 | 2010 |
| The RISC-V Reader: an open architecture Atlas D Patterson, A Waterman Strawberry Canyon, 2017 | 110 | 2017 |
| A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ... IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016 | 74 | 2016 |
| The risc-v instruction set manual, volume i: Base user-level isa. EECS Department A Waterman, Y Lee, DA Patterson, K Asanovic University of California, 2011 | 56 | 2011 |
| A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015 | 49 | 2015 |
| Processes and resource management in a scalable many-core OS K Klues, B Rhoden, Y Zhu, A Waterman, E Brewer HotPar10, Berkeley, CA, 106-109, 2010 | 47 | 2010 |
Krste AsanovicUC BerkeleyVerified email at berkeley.edu
