Jofre Pallares
Jofre Pallares
IMB-CNM (CSIC)
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All-inkjet-printed thin-film transistors: manufacturing process reliability by root cause analysis
E Sowade, E Ramon, KY Mitra, C Martínez-Domingo, M Pedró, J Pallarès, ...
Scientific reports 6, 33490, 2016
542016
A 25-µw all-mos potentiostatic delta-sigma adc for smart electrochemical sensors
S Sutula, JP Cuxart, J Gonzalo-Ruiz, FX Muñoz-Pascual, L Terés, ...
IEEE Transactions on circuits and systems I: Regular Papers 61 (3), 671-679, 2014
242014
Development of a standard cell library and ASPEC design flow for organic thin film transistor technology
M Mashayekhi, M Llamas, J Carrabina, J Pallarès, F Vila, L Terés
Design of Circuits and Integrated Systems, 1-6, 2014
122014
Inkjet-configurable gate arrays (IGA)
J Carrabina, M Mashayekhi, J Pallares, L Teres
IEEE Transactions on Emerging Topics in Computing 5 (2), 238-246, 2016
102016
PCell based devices & structures for Printed Electronics and related semiautomatic characterization loop
A Conde, J Pallarès, L Terés, C Martínez, E Ramon, J Carrabina
Proceedings of the XVIII Conference on the Design of Circuits and Integrated …, 2013
82013
Micro-electromechanical switch, method of manufacturing an integrated circuit including at least one such switch, and an integrated circuit
J Cuxart
US Patent App. 11/582,948, 2007
82007
Top-down design flow for application specific printed electronics circuits (ASPECs)
M Llamas, M Mashayekhi, J Carrabina, J Pallares, F Vila, L Teres
Design of Circuits and Integrated Systems, 1-5, 2014
62014
A 1.2 V 130μA 10-bit MOS-Only Log-Domain ΣΔ Modulator
X Redondo, J Pallares, F Serra-Graells
2007 IEEE International Symposium on Circuits and Systems, 17-20, 2007
62007
Large-area automated layout extraction methodology for full-ic reverse engineering
R Quijada, R Dura, J Pallares, X Formatje, S Hidalgo, F Serra-Graells
Journal of Hardware and Systems Security 2 (4), 322-332, 2018
52018
Fault-tolerant inkjet gate array for application specific printed electronic circuits
M Mashayekhi, M Llamas, J Pallarès, F Vila, L Terés, J Carrabina
6th International Conference on Computer Aided Design for Thin-Film …, 2014
52014
Teaching mixed-mode full-custom VLSI design with gaf, SpiceOpus and Glade
S Sutula, F Vila, J Pallarès, K Sabine, L Terés, F Serra-Graells
10th European Workshop on Microelectronics Education (EWME), 43-48, 2014
52014
Electrostatic actuation method and electrostatic actuator with integral electrodes for microelectromechanical systems
M Flores, J Cuxart
US Patent App. 11/717,803, 2007
42007
A systematic study of pattern compensation methods for all-inkjet printing processes
F Vila, J Pallares, E Ramon, L Teres
IEEE Transactions on Components, Packaging and Manufacturing Technology 6 (4 …, 2016
32016
Development of Digital Application Specific Printed Electronics Circuits: From Specification to Final Prototypes
M Llamas, M Mashayekhi, A Alcalde, J Carrabina, J Pallarès, F Vila, ...
Journal of Display Technology 11 (8), 652-657, 2015
32015
A fully-automated methodology and system for printed electronics foil characterization
F Vila, J Pallarès, A Conde, L Terés
Proceedings of the 2015 International Conference on Microelectronic Test …, 2015
32015
Large-scale fabrication of all-inkjet printed organic thin film transistors: a quantitative study
E Ramon, C Martínez-Domingo, A Alcalde-Aragonés, J Carrabina, ...
NIP & Digital Fabrication Conference 2014 (1), 455-460, 2014
32014
MODELING ALL-MOS LOG FILTERS AND ITS APPLICATION TO SIGMA-DELTA MODULATORS
J Pallares, J Sabadell, F Serra-Graells
IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, I-117, 2003
32003
fast and robust Topology-Based logic gate identification for automated IC reverse engineering
R Durà, J Pallarès, R Quijada, X Formatjé, S Hidalgo, F Serra-Graells
ISTFA 2017: Proceedings from the 43rd International Symposium for Testing …, 2017
22017
An academic EDA suite for the full-custom design of mixed-mode integrated circuits
J Pallarès, K Sabine, L Terés, F Serra-Graells
2017 IEEE international symposium on circuits and systems (ISCAS), 1-4, 2017
22017
A complete suite of open/free EDA tools for PE physical design
F Vila, J Pallarès, L Teres, J Carrabina, K Sabine
DATE, 2013
22013
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