A process-tolerant cache architecture for improved yield in nanoscale technologies A Agarwal, BC Paul, H Mahmoodi, A Datta, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (1), 27-38, 2005 | 265 | 2005 |
Modeling and circuit synthesis for independently controlled double gate FinFET devices A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy IEEE Transactions on Computer-aided Design of Integrated circuits and …, 2007 | 117 | 2007 |
Speed binning aware design methodology to improve profit under parameter variations A Datta, S Bhunia, JH Choi, S Mukhopadhyay, K Roy Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 58 | 2006 |
Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies A Datta, S Bhunia, S Mukhopadhyay, N Banerjee, K Roy Design, Automation and Test in Europe, 926-931, 2005 | 41 | 2005 |
Shared-diffusion standard cell architecture P Kamal, E Terzioglu, F Vang, PB Patel, G Nallapati, A Datta US Patent 8,836,040, 2014 | 25 | 2014 |
Systems and methods using improved clock gating cells A Datta, M Saint-Laurent, V Verma, PB Patel US Patent 8,030,982, 2011 | 25 | 2011 |
Profit aware circuit design under process variations considering speed binning A Datta, S Bhunia, JH Choi, S Mukhopadhyay, K Roy IEEE Transactions on very Large Scale Integration (vlsi) systems 16 (7), 806-815, 2008 | 25 | 2008 |
Delay modeling and statistical design of pipelined circuit under process variation A Datta, S Bhunia, S Mukhopadhyay, K Roy IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 22 | 2006 |
Self-repairing SRAM for reducing parametric failures in nanoscaled memory S Mukhopadhyay, K Kim, H Mahmoodi, A Datta, D Park, K Roy 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 132-133, 2006 | 22 | 2006 |
Digital circuit design with semi-continuous diffusion standard cell X Chen, O Kwon, S Satyanarayana, D Gangadharan, CI Kao, ... US Patent 9,190,405, 2015 | 17 | 2015 |
Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices PR Chidambaram, C Gan, S Sengupta, L Ge, Y Chen, S Yang, P Liu, ... 2010 International Electron Devices Meeting, 27.3. 1-27.3. 4, 2010 | 17 | 2010 |
Layout construction for addressing electromigration SH Rasouli, MJ Brunolli, CSA Hau-Riege, M Malabry, SK Harish, ... US Patent 9,972,624, 2018 | 16 | 2018 |
Adaptive standard cell architecture and layout techniques for low area digital SoC JM Shah, K Medisetti, V Ranganna, A Datta US Patent 9,070,552, 2015 | 16 | 2015 |
GAARP: a power-aware GALS architecture for real-time algorithm-specific tasks S Bhunia, A Datta, N Banerjee, K Roy IEEE Transactions on Computers 54 (6), 752-766, 2005 | 16 | 2005 |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology M Saint-Laurent, A Datta Proceedings of the 16th ACM/IEEE international symposium on Low power …, 2010 | 15 | 2010 |
Copper (II)-promoted oxidation/[3+ 2] cycloaddition/aromatization cascade: efficient synthesis of tetrasubstituted NH-pyrrole from chalcones and iminodiacetates Z Lin, C Li, Z Zhou, S Xue, J Gao, Q Ye, Y Li Synlett 30 (12), 1442-1446, 2019 | 14 | 2019 |
Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation LJ Mishra, DT Chun, A Datta US Patent 9,875,209, 2018 | 13 | 2018 |
High performance standard cell with continuous oxide definition and characterized leakage current X Chen, O Kwon, F Vang, A Datta, SH Rasouli US Patent 9,318,476, 2016 | 13 | 2016 |
Clock-gating cell with low area, low power, and low setup time SH Rasouli, SJ Dillen, A Datta US Patent 9,577,635, 2017 | 12 | 2017 |
Plasmon–Phonon Coupling in Electrostatically Gated β-Ga2O3 Films with Mobility Exceeding 200 cm2 V–1 s–1 AK Rajapitamahuni, AK Manjeshwar, A Kumar, A Datta, P Ranga, ... ACS nano 16 (6), 8812-8819, 2022 | 10 | 2022 |