| HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs S Campanoni, K Brownell, S Kanev, TM Jones, GY Wei, D Brooks | 77 | 2014 |
| Evaluation of voltage interpolation to address process variations K Brownell, GY Wei, D Brooks 2008 IEEE/ACM International Conference on Computer-Aided Design, 529-536, 2008 | 14 | 2008 |
| Methods and apparatus for executing data-dependent threads in parallel GY Wei, DM Brooks, S Campanoni, KM Brownell, S Kanev US Patent 10,949,200, 2021 | 12 | 2021 |
| Automating design of voltage interpolation to address process variations KM Brownell, AD Khan, GY Wei, D Brooks IEEE transactions on very large scale integration (VLSI) systems 19 (3), 383-396, 2009 | 3 | 2009 |
| Automatically accelerating non-numerical programs by architecture-compiler co-design S Campanoni, K Brownell, S Kanev, TM Jones, GY Wei, D Brooks Communications of the ACM 60 (12), 88-97, 2017 | 1 | 2017 |
| Architectural Implications of Automatic Parallelization With HELIX-RC KM Brownell | 1 | 2015 |
| Breaking Cyclic-Multithreading Parallelization with XML Parsing S Campanoni, S Kanev, K Brownell, D Brooks, GY Wei PRISM, 2014 | 1 | 2014 |
| Place and route considerations for voltage interpolated designs K Brownell, AD Khan, D Brooks, GY Wei 2009 10th International Symposium on Quality Electronic Design, 594-600, 2009 | 1 | 2009 |
Simone CampanoniNorthwestern UniversityEmail confirmado em northwestern.edu
