Jose S. Matos
Jose S. Matos
Email confirmado em fe.up.pt
TítuloCitado porAno
A boundary scan test controller for hierarchical BIST
JS Matos, FS Pinto, JMM Ferreira
Test Conference, 1992. Proceedings., International, 217, 1995
331995
A boundary scan test controller for hierarchical BIST
JMM Ferreira, FS Pinto, JS Matos
Proceedings of the IEEE International Test Conference on Discover the New …, 1992
33*1992
Control and observation of analog nodes in mixed-signal boards
JS Matos, AC Leão, JC Ferreira
Test Conference, 1993. Proceedings., International, 323-331, 1993
291993
Cross-correlation between iDD and vOUT signals for testing analogue circuits
JM da Silva, JS Matos, IM Bell, GE Taylor
Electronics Letters 31 (19), 1617-1618, 1995
171995
RVC - A Reconfigurable Coprocessor for Vector Processing Applications
JC Alves, JS Matos
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing …, 1998
151998
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits
JM Da Silva, JS Matos, IM Bell, GE Taylor
Journal of Electronic Testing 9 (1-2), 75-88, 1996
151996
Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
JMM Ferreira, JS Matos, FS Pinto
Design Automation, 1992. Proceedings.,[3rd] European Conference on, 154-158, 1992
151992
Boundary scan test, test methodology, and fault modeling
F De Jong, JS Matos, JM Ferreira
Journal of Electronic Testing 2 (1), 77-88, 1991
131991
Binary decision diagrams: From abstract representations to physical implementations
JS Matos, JV Oldfield
Proceedings of the 20th Design Automation Conference, 567-570, 1983
131983
A comparison of ADC dynamic test methods
HS Mendonça, JM Silva, JS Matos
Proc. Design of Circuits and Integrated Systems Conference, 102-107, 2000
112000
Evaluation of i DD/v OUT cross-correlation for mixed current-voltage testing of analogue and mixed-signal circuits
JM Da Silva, JS Matos
European Design and Test Conference, 1996. ED&TC 96. Proceedings, 264-268, 1996
91996
ADC testing using joint time–frequency analysis
H Mendonça, JM da Silva, JS Matos
Computer Standards & Interfaces 23 (2), 129-135, 2001
52001
Mixed-signal BIST using correlation and reconfigurable hardware
JM da Silva, JS Duarte, JS Matos
Design, Automation and Test in Europe Conference and Exhibition 2000 …, 2000
5*2000
Architecture of test support ICs for mixed-signal testing
JS Matos, JC Ferreira, AC Leão, JM Silva
VLSI Test Symposium, 1994. Proceedings., 12th IEEE, 240-246, 1994
51994
Design for Embedded Testing of an LNA
JM da Silva, A Pinho, JS Matos
XX Design of Circuits and Integrated Systems, 2005
42005
Functional in-circuit characterisation of ΣΔ modulators
JM da Silva, JS Duarte, JS Matos
Measurement 32 (4), 257-264, 2002
42002
A tool for fault extraction in pcbs
LC Laranjeira, JM da Silva, JS Matos
Proc. European Test Workshop 2000, 2000
42000
Flexible hardware acceleration for nesting problems
JC Ferreira, JC Alves, C Albuquerque, JF Oliveira, JS Ferreira, JS Matos
Electronics, Circuits and Systems, 1998 IEEE International Conference on 1 …, 1998
41998
A vector architecture for higher-order moments estimation
JC Alves, A Puga, L Corte-Real, JS Matos
Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE …, 1997
41997
A simulated annealing approach for high-level synthesis with reconfigurable functional units
JC Alves, JS Matos
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest …, 1995
41995
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