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Uday Reddy Bondhugula
Uday Reddy Bondhugula
Indian Institute of Science and PolyMage Labs
Email confirmado em iisc.ac.in - Página inicial
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A practical automatic polyhedral parallelizer and locality optimizer
U Bondhugula, A Hartono, J Ramanujam, P Sadayappan
ACM SIGPLAN conference on Programming Languages Design and Implementation 43 …, 2008
1339*2008
Automatic transformations for communication-minimized parallelization and locality optimization in the polyhedral model
U Bondhugula, M Baskaran, S Krishnamoorthy, J Ramanujam, A Rountev, ...
International Conference on Compiler Construction, 132-146, 2008
3252008
A compiler framework for optimization of affine loop nests for GPGPUs
MM Baskaran, U Bondhugula, S Krishnamoorthy, J Ramanujam, ...
Proceedings of the 22nd annual international conference on Supercomputing …, 2008
2892008
Effective automatic parallelization of stencil computations
S Krishnamoorthy, M Baskaran, U Bondhugula, J Ramanujam, A Rountev, ...
ACM SIGPLAN conference on Programming Language Design and Implementation …, 2007
2882007
Tiling stencil computations to maximize parallelism
V Bandishti, I Pananilath, U Bondhugula
SC'12: Proceedings of the International Conference on High Performance …, 2012
2252012
Polymage: Automatic optimization for image processing pipelines
RT Mullapudi, V Vasista, U Bondhugula
International conference on Architectural Support for Programming Languages …, 2015
2132015
Loop transformations: convexity, pruning and optimization
LN Pouchet, U Bondhugula, C Bastoul, A Cohen, J Ramanujam, ...
ACM SIGPLAN Notices 46 (1), 549-562, 2011
1632011
Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories
MM Baskaran, U Bondhugula, S Krishnamoorthy, J Ramanujam, ...
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of …, 2008
1552008
MLIR: A Compiler Infrastructure for the End of Moore's Law
C Lattner, M Amini, U Bondhugula, A Cohen, A Davis, J Pienaar, R Riddle, ...
arXiv preprint arXiv:2002.11054, 2020
1352020
Combined iterative and model-driven optimization in an automatic parallelization framework
LN Pouchet, U Bondhugula, C Bastoul, A Cohen, J Ramanujam, ...
SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010
121*2010
Compiling affine loop nests for distributed-memory parallel architectures
U Bondhugula
SC'13: Proceedings of the International Conference on High Performance …, 2013
115*2013
Effective automatic parallelization and locality optimization using the polyhedral model
UK Bondhugula
The Ohio State University, 2008
1042008
Data layout transformation for enhancing data locality on NUCA chip multiprocessors
Q Lu, C Alias, U Bondhugula, T Henretty, S Krishnamoorthy, ...
Parallel Architectures and Compilation Techniques, 2009. PACT'09. 18th …, 2009
992009
Parallel FPGA-based all-pairs shortest-paths in a directed graph
U Bondhugula, A Devulapalli, J Fernando, P Wyckoff, P Sadayappan
Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006
892006
A model for fusion and code motion in an automatic parallelizing compiler
U Bondhugula, S Dash, O Gunluk, L Renganarayanan
2010 19th International Conference on Parallel Architectures and Compilation …, 2010
832010
Mlir: Scaling compiler infrastructure for domain specific computation
C Lattner, M Amini, U Bondhugula, A Cohen, A Davis, J Pienaar, R Riddle, ...
2021 IEEE/ACM International Symposium on Code Generation and Optimization …, 2021
812021
Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors
MM Baskaran, N Vydyanathan, UKR Bondhugula, J Ramanujam, ...
ACM sigplan notices 44 (4), 219-228, 2009
792009
Pluto: A practical and fully automatic polyhedral parallelizer and locality optimizer
U Bondhugula, J Ramanujam, P Sadayappan
The Ohio State University, 2007
652007
Diamond tiling: Tiling techniques to maximize parallelism for stencil computations
U Bondhugula, V Bandishti, I Pananilath
IEEE Transactions on Parallel and Distributed Systems 28 (5), 1285-1298, 2016
632016
A DSL compiler for accelerating image processing pipelines on FPGAs
N Chugh, V Vasista, S Purini, U Bondhugula
Proceedings of the 2016 International Conference on Parallel Architectures …, 2016
582016
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