Simone Campanoni
Simone Campanoni
Assistant professor at Northwestern University
Email confirmado em - Página inicial
TítuloCitado porAno
HELIX: Automatic Parallelization of Irregular Programs for Chip Multiprocessing
S Campanoni, T Jones, G Holloway, VJ Reddi, GY Wei, D Brooks
CGO, 2012
Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling
VJ Reddi, S Kanev, W Kim, S Campanoni, MD Smith, GY Wei, D Brooks
Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on …, 2010
Metronome: operating system level performance management via self-adaptive computing
F Sironi, DB Bartolini, S Campanoni, F Cancare, H Hoffmann, D Sciuto, ...
Proceedings of the 49th Annual Design Automation Conference, 856-865, 2012
HELIX-RC: An Architecture-Compiler Co-Design for Automatic Parallelization of Irregular Programs
S Campanoni, K Brownell, S Kanev, T Jones, GY Wei, D Brooks
ISCA, 2014
HELIX-UP: Relaxing program semantics to unleash parallelization
S Campanoni, G Holloway, GY Wei, D Brooks
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code …, 2015
A highly flexible, parallel virtual machine: design and experience of ILDJIT
S Campanoni, G Agosta, S Crespi Reghizzi, A Di Biagio
Software: Practice and Experience 40 (2), 177-207, 2010
Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack
VJ Reddi, MS Gupta, MD Smith, G Wei, D Brooks, S Campanoni
2009 46th ACM/IEEE Design Automation Conference, 788-793, 2009
Voltage noise in production processors
VJ Reddi, S Kanev, W Kim, S Campanoni, MD Smith, GY Wei, D Brooks
IEEE micro 31 (1), 20-28, 2010
HELIX: Making the extraction of thread-level parallelism mainstream
S Campanoni, TM Jones, G Holloway, GY Wei, D Brooks
IEEE Micro 32 (4), 8-18, 2012
Eliminating voltage emergencies via software-guided code transformations
VJ Reddi, S Campanoni, MS Gupta, MD Smith, GY Wei, D Brooks, ...
ACM Transactions on Architecture and Code Optimization (TACO) 7 (2), 12, 2010
Dynamic look ahead compilation: a technique to hide JIT compilation latencies in multicore environment
S Campanoni, M Sykora, G Agosta, SC Reghizzi
International conference on compiler construction, 220-235, 2009
A parallel dynamic compiler for CIL bytecode
S Campanoni, G Agosta, S Reghizzi
SIGPLAN Notices 43 (4), 11-20, 2008
Voltage noise: Why it’s bad, and what to do about it
VJ Reddi, MS Gupta, KK Rangan, S Campanoni, G Holloway, MD Smith, ...
5th IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE), Palo …, 2009
Performance implications of transient loop-carried data dependences in automatically parallelized loops
N Murphy, T Jones, R Mullins, S Campanoni
Proceedings of the 25th International Conference on Compiler Construction, 23-33, 2016
Methods and apparatus for parallel processing
GY Wei, DM Brooks, S Campanoni, KM Brownell, S Kanev
US Patent App. 14/898,894, 2016
The helix project: Overview and directions
S Campanoni, T Jones, G Holloway, GY Wei, D Brooks
DAC Design Automation Conference 2012, 277-282, 2012
Just-In-Time compilation on ARM processors
M Tartara, S Campanoni, G Agosta, SC Reghizzi
4th Workshop on the Implementation, Compilation, Optimization of Object …, 2009
SWORDFISH: A framework to formally design WSNs capturing events
S Campanoni, W Fornaciari
2007 15th International Conference on Software, Telecommunications and …, 2007
Temporal Approximate Function Memoization
G Tziantzioulis, N Hardavellas, S Campanoni
IEEE Micro 38 (4), 60-70, 2018
Compiler-guided instruction-level clock scheduling for timing speculative processors
Y Fan, T Jia, J Gu, S Campanoni, R Joseph
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
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