Rasika Dhavse
Rasika Dhavse
Associate Professor, Electronics Engineering Department, SVNIT, Surat
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Cited by
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Design of operational transconductance amplifier using 0.35 µm technology
BH Soni, RN Dhavse
Int. J. Wisdom Based Comput 1 (2), 28-31, 2011
Mobile controlled robots for regulating DC motors and their domestic applications
S Khakurel, AK Ojha, S Shrestha, RN Dhavse
International Journal of Scientific & Engineering Research 1 (3), 1-5, 2010
Strategic reduction of area and power in FIR filter architecture for ECG signal acquisition
S Janwadkar, R Dhavse
2020 IEEE 17th India Council International Conference (INDICON), 1-7, 2020
Qualitative and quantitative analysis of parallel-prefix adders
S Janwadkar, R Dhavse
Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019, 71-88, 2020
Novel hybrid silicon SETMOS design for power efficient room temperature operation
R Shah, R Dhavse
Silicon 13 (2), 587-597, 2021
Power and area efficient FIR filter architecture in digital encephalography systems
S Janwadkar, R Dhavse
E-Prime-Advances in Electrical Engineering, Electronics and Energy 4, 100148, 2023
Development of Micro-Machined Porous-Silicon Capacitive Chip for Quantification & Sensing of Organic Solvents
SM Gheewala, C Parmesh, PN Patel, R Dhavse
Solid State Technology 64 (2), 4725-4739, 2021
Fabrication and Investigation of Low Voltage Programmable Flash Memory Gate Stack
Lecture Notes in Electrical Engineering 453, 35-49, 2018
Memory characteristics of a 65 nm FGMOS capacitor with Si quantum dots as floating gates
R Dhavse, F Muhammed, C Sinha, V Mishra, RM Patrikar
2013 Annual IEEE India Conference (INDICON), 1-3, 2013
Comparison of total ionizing dose effect on tolerance of SCL 180 nm bulk and SOI CMOS using TCAD simulation
S Anjankar, R Dhavse
Emerging Technology Trends in Electronics, Communication and Networking …, 2022
Radiation sensor design for mitigation of total ionizing dose effects
S Anjankar, R Dhavse
Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2021, 267-279, 2022
Investigation and analysis of power performance area (ppa) cards of digital multiplier architectures
S Janwadkar, R Dhavse
Journal of Circuits, Systems and Computers 31 (13), 2250239, 2022
Strategic design and optimization of Vedic low pass FIR filter for ECG signals
S Janwadkar, R Dhavse
Proceeding of Fifth International Conference on Microelectronics, Computing …, 2021
Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Operating at Room Temperature
A Sharma, R Dhavse, Y Agrawal, R Parekh
Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019, 201-209, 2021
Precise, portable and wide band alternating current source for extremely low current values
S Sruthi, R Dhavse, JN Sarvaiya
Analog Integrated Circuits and Signal Processing 102 (2), 273-282, 2020
Tunnel Barrier Optimization for Room Temperature Operation of Single Electron Transistors
RD Raj Shah
SETCOR International Conference Nanotech France 2018, DOI: …, 2018
Innovative leakage stabilisation system for mitigation of ionising radiation-induced effects
S Anjankar, R Dhavse
IEEE Sensors Letters, 2023
Design & development of laser etched porous-silicon capacitive chip for rapid sensing of pesticide solvents
SM Gheewala, C Parmesh, PN Patel, R Dhavse
Silicon, 1-11, 2021
Simulation and Fabrication of Macro Porous Silicon for Highly Chemicapacitive Detection for Aqueous Solvent
SM Gheewala, C Parmesh, PN Patel, R Dhavse
Journal of Sensor Research and Technologies 3 (2), 2021
Design strategy and simulation of single-gate SET for novel SETMOS hybridization
R Shah, R Parekh, R Dhavse
Journal of Computational Electronics 20 (1), 218-229, 2021
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