| Defect level evaluation in an IC design environment JT De Sousa, FM Gonçalves, JP Teixeira, C Marzocca, F Corsi, ... IEEE transactions on computer-aided design of integrated circuits and …, 1996 | 66 | 1996 |
| A SAT Solver using Reconfigurable Hardware and Virtual Logic M Abramovici, J.T. de Sousa SAT 2000, Highlights of Satisfiability Research in the Year 2000,, 377-402, 2001 | 49 | 2001 |
| A SAT solver using reconfigurable hardware and virtual logic M Abramovici, JT De Sousa Journal of Automated Reasoning 24 (1), 5-36, 2000 | 49 | 2000 |
| IC Defects-Based Testability Analysis JJT Sousa, FM Gonçalves, ... International Test Conference (ITC), 500-509, 1991 | 46 | 1991 |
| A configurable hardware/software approach to SAT solving JT de Sousa, JM Da Silva, M Abramovici The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001 | 44 | 2001 |
| A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware M Abramovici, JT de Sousa, D Saab Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 684-690, 1999 | 43 | 1999 |
| Virtual logic system for solving satisfiability problems using reconfigurable hardware M Abramovici, JT De Sousa US Patent 6,442,732, 2002 | 41 | 2002 |
| Parallel backtracing for satisfiability on reconfigurable hardware M Abramovici, JT De Sousa, DG Saab US Patent 6,292,916, 2001 | 34 | 2001 |
| Reducing the complexity of defect level modeling using the clustering effect JT de Sousa, VD Agrawal Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000 | 32 | 2000 |
| Network core access architecture JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins US Patent 8,019,832, 2011 | 31 | 2011 |
| Physical DFT for High Coverage of Realistic Faults M Saraiva, P Casimiro, M Santos, JT Sousa, FM Gonçalves, I Teixeira, ... Int. Test Conference (ITC), 642-651, 1992 | 27 | 1992 |
| Physical design of testable CMOS digital integrated circuits JJHT de Sousa, FM Goncalves, JP Teixeira IEEE Journal of Solid State Circuits 26 (7), 1064-1072, 1991 | 21 | 1991 |
| Fault Modeling and Defect Level Projections in Digital ICs JT Sousa, FM Gonçalves, JP Teixeira, TW Williams European Design and Test Conference (ED&TC), 436-442, 1994 | 20 | 1994 |
| On implementing a configware/software SAT solver NA Reis, JT de Sousa Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom …, 2002 | 19 | 2002 |
| Fault simulation using partially reconfigurable hardware A Parreira, JP Teixeira, A Pantelimon, MB Santos, JT de Sousa International Conference on Field Programmable Logic and Applications, 839-848, 2003 | 18 | 2003 |
| Parallel Dot-Products for Deep Learning on FPGA M Véstias, R Duarte, JT de Sousa, H Neto 27th Int. Conference on Field Programmable Logic and Applications, 2017 | 16 | 2017 |
| Heuristic backtracking algorithms for SAT A Bhalla, I Lynce, JT de Sousa, J Marques-Silva Proceedings. 4th International Workshop on Microprocessor Test and …, 2003 | 16 | 2003 |
| Layout-Driven Testability Enhancement JP Teixeira, FM Gonçalves, JJT Sousa European Test Conference, 101-109, 1991 | 16 | 1991 |
| Defect Level Estimation for Digital ICs JJT Sousa, JP Teixeira IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, 32-41, 1992 | 14 | 1992 |
| Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs HN Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa 28th International Conference on Field Programmable Logic and Applications (FPL), 2018 | 13 | 2018 |
Paulo TeixeiraINESC-ID, IST, Univ. Lisboa, PortugalEmail confirmado em ist.utl.pt
