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Prof. (Dr.) Priyadarsan Patra
Prof. (Dr.) Priyadarsan Patra
Pro Vice-Chancellor and Distinguished Professor, DIT University
Email confirmado em seedsnet.org - Página inicial
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Low-power High-level Synthesis for Nanoscale CMOS Circuits
SP Mohanty, N Ranganathan, E Kougianos, P Patra
Springer, ISBN: 978-0-387-76474-0, 2008
1242008
On the cusp of a validation wall
P Patra
IEEE Design & Test of Computers 24 (2), 193-196, 2007
1152007
Impact of process and temperature variations on network-on-chip design exploration
B Li, LS Peh, P Patra
Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 117-126, 2008
882008
A design for digital, dynamic clock deskew
CE Dike, NA Kurd, P Patra, J Barkatullah
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2003
572003
Runtime validation of memory ordering using constraint graph checking
K Chen, S Malik, P Patra
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
532008
A course recommendation system based on grades
B Mondal, O Patra, S Mishra, P Patra
IEEE, 2019
422019
Test, validation, and debug architecture
MB Trobough, KK Tiruvallur, CB Prudvi, CE Iovin, DW Grawrock, ...
US Patent 10,198,333, 2019
412019
Efficient combination of trace and scan signals for post silicon validation and debug
K Basu, P Mishra, P Patra
2011 IEEE International Test Conference, 1-8, 2011
412011
Efficient building blocks for delay insensitive circuits
P Patra, DS Fussell
Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous …, 1994
401994
Delay insensitive logic for RSFQ superconductor technology
P Patra, S Polonsky, DS Fussell
Proceedings Third International Symposium on Advanced Research in …, 1997
331997
Noise and power optimization in high performance circuits
P Patra, B Chappell
US Patent App. US 09/964,803, 2001
302001
On efficient adiabatic design of MOS circuits
P Patra, D Fussell
Workshop on Physics and Computation, Boston, 260-269, 1996
281996
Automated phase assignment for the synthesis of low power domino circuits
P Patra, U Narayanan
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 379-384, 1999
271999
A novel performance-driven topology design algorithm
M Pan, C Chu, P Patra
2007 Asia and South Pacific Design Automation Conference, 244-249, 2007
262007
Conservative delay-insensitive circuits
P Patra, DS Fussell
Workshop on Physics and Computation, 248-259, 1996
261996
Approaches to design of circuits for low-power computation
P Patra
The University of Texas at Austin, 1995
261995
Dynamic selection of trace signals for post-silicon debug
K Basu, P Mishra, P Patra, A Nahir, A Adir
2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013
252013
Building-blocks for designing DI circuits
P Patra, DS Fussell
University of Texas at Austin, Department of Computer Sciences, 1993
211993
Power consumption reduction for domino circuits
P Patra, UK Narayanan
US Patent 6,529,861, 2003
192003
Nano-cmos mixed-signal circuit metamodeling techniques: A comparative study
O Garitselov, SP Mohanty, E Kougianos, P Patra
2010 International Symposium on Electronic System Design, 191-196, 2010
162010
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