Nuno Lourenço
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LAYGEN II—Automatic layout generation of analog integrated circuits
R Martins, N Lourenco, N Horta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
772013
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
N Lourenço, N Horta
Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012
522012
AIDA: Automated analog IC design flow from circuit level to layout
R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
432012
AIDA:Layout-aware analog circuit level sizing with in-loop layout generation
N Lourenço, R Martins, A Canelas, R Póvoa, N Horta
Integration, the VLSI Journal, 2016
36*2016
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction
N Lourenço, R Martins, N Horta
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
322015
Floorplan-aware analog IC sizing and optimization based on topological constraints
N Lourenço, A Canelas, R Póvoa, R Martins, N Horta
Integration 48, 183-197, 2015
322015
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques
R Povoa, I Bastos, N Lourenço, N Horta
Integration 52, 243-252, 2016
312016
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
R Martins, N Lourenço, A Canelas, R Póvoa, N Horta
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
312015
Network core access architecture
JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins
US Patent 8,019,832, 2011
312011
Laygen-automatic layout generation of analog ics from hierarchical template descriptions
N Lourenço, M Vianello, J Guilherme, N Horta
2006 Ph. D. Research in Microelectronics and Electronics, 213-216, 2006
282006
Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates
R Martins, N Lourenço, N Horta
Expert Systems with Applications 42 (23), 9137-9151, 2015
272015
Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
N Lourenço, R Martins, N Horta
Springer International Publishing, 2017
262017
Electromigration-aware analog Router with multilayer multiport terminal structures
R Martins, N Lourenco, A Canelas, N Horta
Integration 47 (4), 532-547, 2014
232014
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners
R Povoa, N Lourenço, N Horta, R Santos-Tavares, J Goes
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013
222013
Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop
R Martins, N Lourenço, F Passos, R Póvoa, A Canelas, E Roca, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
202018
LC-VCO automatic synthesis using multi-objective evolutionary techniques
R Póvoa, R Lourenço, N Lourenço, A Canelas, R Martins, N Horta
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 293-296, 2014
182014
Analog Integrated Circuit Design Automation
R Martins, N Lourenço, N Horta
Springer, 2017
172017
Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications
R Martins, N Lourenço, N Horta, J Yin, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018
152018
Electromigration-aware and IR-drop avoidance routing in analog multiport terminal structures
R Martins, N Lourenço, A Canelas, N Horta
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
152014
Laygen ii: automatic analog ics layout generator based on a template approach
R Martins, N Lourenço, N Horta
Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012
152012
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