Daniel Grosse

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Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyEmail confirmado em uni-bremen.de
Robert WilleTechnical University of Munich and SCCH GmbHEmail confirmado em tum.de
Hoang M. LeUniversity of BremenEmail confirmado em informatik.uni-bremen.de
Vladimir HerdtSenior Researcher at University of Bremen / DFKI GmbHEmail confirmado em uni-bremen.de
Ulrich KühneTélécom ParisTechEmail confirmado em telecom-paristech.fr
Gerhard W DueckProfessor of Computer Science, University of New BrunswickEmail confirmado em unb.ca
Mathias SoekenMicrosoftEmail confirmado em epfl.ch
Arun ChandrasekharanGraduate Student, Group of Computer Architecture, University of Bremen, GermanyEmail confirmado em cs.uni-bremen.de
Goerschwin FeyHamburg University of TechnologyEmail confirmado em tuhh.de
Marcel WalterTechnical University of MunichEmail confirmado em tum.de
Frank Sill Torres; Frank Sill; FS Torres;...German Aerospace Center (DLR) / Institute for the Protection of Maritime InfrastructuresEmail confirmado em ufmg.br
Alireza MahzoonUniversity of BremenEmail confirmado em informatik.uni-bremen.de
Muhammad HassanUniversity of BremenEmail confirmado em uni-bremen.de
Saman FröhlichUniversität Bremen, AGRAEmail confirmado em uni-bremen.de
Stefan FrehseEmail confirmado em mailbox.org
Amr Sayed AhmedARMEmail confirmado em arm.com
Melanie DiepenbeckResearcher, Bremen UniversityEmail confirmado em informatik.uni-bremen.de
Stephan EggersglüßMentor, A Siemens BusinessEmail confirmado em mentor.com
Mehran GoliPhD - Computer Science, University of BremenEmail confirmado em uni-bremen.de
Pascal PieperDeutsches Zentrum für künstliche Intelligenz, Uni BremenEmail confirmado em DFKI.de

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Daniel Grosse

Full Professor at Johannes Kepler University Linz

Email confirmado em jku.at - Página inicial

embedded systems virtual prototyping verification RISC-V SystemC


Título Ordenar por citações Ordenar por ano Ordenar por título	Citado por Citado por	Ano
RevLib: An online resource for reversible functions and reversible circuits R Wille, D Große, L Teuber, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 220-225, 2008	461	2008
Exact multiple-control Toffoli network synthesis with SAT techniques D Große, R Wille, GW Dueck, R Drechsler IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009	205	2009
Proving transaction and system-level properties of untimed SystemC TLM designs D Große, HM Le, R Drechsler Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010	98	2010
Equivalence checking of reversible circuits R Wille, D Große, DM Miller, R Drechsler 2009 39th International Symposium on Multiple-Valued Logic, 324-330, 2009	95	2009
Formal verification of integer multipliers by combining Gröbner basis with logic reduction A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016	83	2016
HW/SW co-verification of embedded systems using bounded model checking D Große, U Kühne, R Drechsler Proceedings of the 16th ACM Great Lakes symposium on VLSI, 43-48, 2006	75	2006
SWORD: A SAT like prover using word level information R Wille, G Fey, D Große, S Eggersglüß, R Drechsler VLSI-SoC: Advanced Topics on Systems on a Chip, 1-17, 2009	65	2009
Formal verification of LTL formulas for SystemC designs D Große, R Drechsler Proceedings of the 2003 International Symposium on Circuits and Systems …, 2003	63	2003
Quantified synthesis of reversible logic R Wille, HM Le, GW Dueck, D Große 2008 Design, Automation and Test in Europe, 1015-1020, 2008	62	2008
Fast exact Toffoli network synthesis of reversible logic R Wille, D Große 2007 IEEE/ACM International Conference on Computer-Aided Design, 60-64, 2007	61	2007
Approximation-aware rewriting of AIGs for error tolerant applications A Chandrasekharan, M Soeken, D Große, R Drechsler 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016	58	2016
BDD minimization for approximate computing M Soeken, D Große, A Chandrasekharan, R Drechsler 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 474-479, 2016	58	2016
Exact SAT-based Toffoli network synthesis D Große, X Chen, GW Dueck, R Drechsler Proceedings of the 17th ACM Great Lakes symposium on VLSI, 96-101, 2007	58	2007
Verifying SystemC using an intermediate verification language and symbolic simulation HM Le, D Große, V Herdt, R Drechsler Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013	57	2013
Reachability analysis for formal verification of SystemC R Drechsler, D Große Proceedings Euromicro Symposium on Digital System Design. Architectures …, 2002	56	2002
Quality-Driven SystemC Design D Große, R Drechsler Springer, 2010	53	2010
Reversible logic synthesis with output permutation R Wille, D Große, GW Dueck, R Drechsler 2009 22nd International Conference on VLSI Design, 189-194, 2009	53	2009
CheckSyC: An efficient property checker for RTL SystemC designs D Große, R Drechsler 2005 IEEE International Symposium on Circuits and Systems, 4167-4170, 2005	52	2005
ParSyC: an efficient SystemC parser G Fey, D Große, T Cassens, C Genz, T Warode, R Drechsler In Workshop on Synthesis And System Integration of Mixed Information …, 2004	52	2004
Exact synthesis of elementary quantum gate circuits for reversible functions with don't cares D Große, R Wille, GW Dueck, R Drechsler 38th International Symposium on Multiple Valued Logic (ismvl 2008), 214-219, 2008	51	2008

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