| VTR 8: High-performance CAD and customizable FPGA architecture modelling KE Murray, O Petelin, S Zhong, JM Wang, M Eldafrawy, JP Legault, E Sha, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (2), 1-55, 2020 | 226 | 2020 |
| Titan: Enabling large and complex benchmarks in academic CAD KE Murray, S Whitty, S Liu, J Luu, V Betz 2013 23rd International Conference on Field programmable Logic and …, 2013 | 137 | 2013 |
| Timing-driven titan: Enabling large benchmarks and exploring the gap between academic and commercial CAD KE Murray, S Whitty, S Liu, J Luu, V Betz ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (2), 1-18, 2015 | 119 | 2015 |
| SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs KE Murray, MA Elgammal, V Betz, T Ansell, K Rothman, A Comodi IEEE Micro 40 (4), 49-57, 2020 | 46 | 2020 |
| AIR: A fast but lazy timing-driven FPGA router KE Murray, S Zhong, V Betz 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 338-344, 2020 | 43 | 2020 |
| RLPlace: Using reinforcement learning and smart perturbations to optimize FPGA placement MA Elgammal, KE Murray, V Betz IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 31 | 2021 |
| Learn to place: FPGA placement using reinforcement learning and directed moves MA Elgamma, KE Murray, V Betz 2020 International Conference on Field-Programmable Technology (ICFPT), 85-93, 2020 | 29 | 2020 |
| Tatum: Parallel timing analysis for faster design cycles and improved optimization KE Murray, V Betz 2018 International Conference on Field-Programmable Technology (FPT), 110-117, 2018 | 26 | 2018 |
| Adaptive FPGA placement optimization via reinforcement learning KE Murray, V Betz 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), 1-6, 2019 | 25 | 2019 |
| Quantifying the cost and benefit of latency insensitive communication on FPGAs KE Murray, V Betz Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 22 | 2014 |
| Optimizing FPGA logic block architectures for arithmetic KE Murray, J Luu, MJP Walker, C McCullough, S Wang, S Huda, B Yan, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 18 | 2020 |
| DNA sequence analysis of the KM19 locus linked to cystic fibrosis: Design of new oligonucleotides to remove non-specific PCR products R Anwar, K Murray, PJ Hedge, JC Smith, AF Markham Human genetics 85 (3), 319-323, 1990 | 17 | 1990 |
| HETRIS: Adaptive floorplanning for heterogeneous FPGAs KE Murray, V Betz 2015 International Conference on Field Programmable Technology (FPT), 88-95, 2015 | 12 | 2015 |
| Jai Min Wang, Mohamed ElDafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G KE Murray, O Petelin, S Zhong Graham, Jean Wu, Matthew JP Walker, Hanqing Zeng, Panagiotis Patros, Jason …, 2020 | 11 | 2020 |
| Calculated risks: Quantifying timing error probability with extended static timing analysis KE Murray, A Suardi, V Betz, G Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 11 | 2018 |
| Incremental costs of hospital-acquired complications in Alberta, Canada T Jackson, A Fong, M Liu, K Murray, L Walz, C Houston, K Walker, S Dean BMC Health Services Research 11, 1-2, 2011 | 9 | 2011 |
| Divide-and-Conquer Techniques for Large Scale FPGA Design KE Murray University of Toronto (Canada), 2015 | 7 | 2015 |
| From Quartus to VPR: Converting HDL to BLIF with the Titan flow KE Murray, S Whitty, S Liu, J Luu, V Betz 2013 23rd International Conference on Field programmable Logic and …, 2013 | 5 | 2013 |
| Quantifying error: Extending static timing analysis with probabilistic transitions KE Murray, A Suardi, V Betz, G Constantinides Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 4 | 2017 |
| Fast and Flexible CAD for FPGAs and Timing Analysis KE Murray University of Toronto (Canada), 2020 | 2 | 2020 |
