| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 366 | 2019 |
| High speed parallel/serial link for data communication RG Gerowitz, CT Gray, J Marshall, CG Riedle, RP Rizzo US Patent 6,222,380, 2001 | 109 | 2001 |
| A 0.54 pJ/b 20 Gb/s ground-referenced single-ended short-reach serial link in 28 nm CMOS for advanced packaging applications JW Poulton, WJ Dally, X Chen, JG Eyles, TH Greer, SG Tell, JM Wilson, ... IEEE Journal of Solid-State Circuits 48 (12), 3206-3218, 2013 | 104 | 2013 |
| Wave Pipelining: Theory and CMOS Implementation: Theory and Cmos Implementation CT Gray, W Liu, RK Cavin III Springer Science & Business Media, 1994 | 103 | 1994 |
| A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020 | 90 | 2020 |
| A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution CT Gray, W Liu, WAM Van Noije, TA Hughes, RK Cavin IEEE Journal of Solid-State Circuits 29 (3), 340-349, 1994 | 90 | 1994 |
| A 250-MHz wave pipelined adder in 2-/spl mu/m CMOS W Liu, CT Gray, D Fan, WJ Farlow, TA Hughes, RK Cavin IEEE Journal of Solid-State Circuits 29 (9), 1117-1128, 1994 | 86 | 1994 |
| Timing constraints for wave-pipelined systems CT Gray, W Liu, RK Cavin IEEE Transactions on computer-aided design of integrated circuits and …, 1994 | 76 | 1994 |
| Analog/mixed-signal hardware error modeling for deep learning inference AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 68 | 2019 |
| A 1.17-pJ/b, 25-Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication using a process-and temperature-adaptive voltage regulator JW Poulton, JM Wilson, WJ Turner, B Zimmer, X Chen, SS Kudva, S Song, ... IEEE Journal of Solid-State Circuits 54 (1), 43-54, 2018 | 64 | 2018 |
| A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019 | 52 | 2019 |
| A 28 nm 2 Mbit 6 T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation ME Sinangil, JW Poulton, MR Fojtik, TH Greer, SG Tell, AJ Gotterba, ... IEEE Journal of Solid-State Circuits 51 (2), 557-567, 2015 | 47 | 2015 |
| A 1.17 pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication in 16nm CMOS using a process-and temperature-adaptive voltage regulator JM Wilson, WJ Turner, JW Poulton, B Zimmer, X Chen, SS Kudva, S Song, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 276-278, 2018 | 45 | 2018 |
| Hardware-enabled artificial intelligence WJ Dally, CT Gray, J Poulton, B Khailany, J Wilson, L Dennison 2018 IEEE Symposium on VLSI Circuits, 3-6, 2018 | 41 | 2018 |
| Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects WJ Turner, JW Poulton, JM Wilson, X Chen, SG Tell, M Fojtik, TH Greer, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 35 | 2018 |
| A CMOS parallel adder using wave pipelining D Fan, C Gray, W Farlow, T Hughes, W Liu, R Cavin Advanced Research in VLSI and Parallel Systems 14, 1992 | 35 | 1992 |
| System that compensates for variances due to process and temperature changes B Buchanan, CT Gray, CG Riedle, RP Rizzo US Patent 6,650,661, 2003 | 31 | 2003 |
| Theoretical and Practical Issues in CMOS Wave Pipelining. CT Gray, TA Hughes, S Arora, W Liu, RK Cavin III VLSI 91, 397-409, 1991 | 31 | 1991 |
| A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18/spl mu/m CMOS technology S Huss, M Mullen, CT Gray, R Smith, M Summers, J Shafer, P Heron, ... Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No …, 2001 | 29 | 2001 |
| Programmable duty cycle distortion generation circuit J Thurston, CT Gray US Patent 8,179,952, 2012 | 26 | 2012 |
