| High-level synthesis of dynamic data structures: A case study using Vivado HLS F Winterstein, S Bayliss, GA Constantinides 2013 International conference on field-programmable technology (FPT), 362-365, 2013 | 124 | 2013 |
| FPGA-based K-means clustering using tree-based data structures F Winterstein, S Bayliss, GA Constantinides 2013 23rd International Conference on Field programmable Logic and …, 2013 | 59 | 2013 |
| MATCHUP: memory abstractions for heap manipulating programs F Winterstein, K Fleming, HJ Yang, S Bayliss, G Constantinides Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | 35 | 2015 |
| An FPGA implementation of the simplex algorithm S Bayliss, GA Constantinides, W Luk 2006 IEEE international conference on field programmable technology, 49-56, 2006 | 35 | 2006 |
| Optimizing SDRAM bandwidth for custom FPGA loop accelerators S Bayliss, GA Constantinides Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012 | 33 | 2012 |
| Offline synthesis of online dependence testing: Parametric loop pipelining for HLS J Liu, S Bayliss, GA Constantinides 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 32 | 2015 |
| Survey of domain-specific languages for FPGA computing N Kapre, S Bayliss 2016 26th International Conference on Field Programmable Logic and …, 2016 | 23 | 2016 |
| Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search S Bayliss, GA Constantinides 2009 International Conference on Field-Programmable Technology, 304-307, 2009 | 23 | 2009 |
| Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs K Shi, D Boland, E Stott, S Bayliss, GA Constantinides 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014 | 21 | 2014 |
| Polyhedral-based dynamic loop pipelining for high-level synthesis J Liu, J Wickerson, S Bayliss, GA Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 20 | 2017 |
| Separation logic-assisted code transformations for efficient high-level synthesis F Winterstein, S Bayliss, GA Constantinides 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 20 | 2014 |
| SOAP: structural optimization of arithmetic expressions for high-level synthesis X Gao, S Bayliss, GA Constantinides 2013 International Conference on Field-Programmable Technology (FPT), 112-119, 2013 | 20 | 2013 |
| GPU vs FPGA: A comparative analysis for non-standard precision UI Minhas, S Bayliss, GA Constantinides International Symposium on Applied Reconfigurable Computing, 298-305, 2014 | 18 | 2014 |
| Application specific memory access, reuse and reordering for SDRAM S Bayliss, GA Constantinides International Symposium on Applied Reconfigurable Computing, 41-52, 2011 | 11 | 2011 |
| Separation logic for high-level synthesis FJ Winterstein, SR Bayliss, GA Constantinides ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (2), 1-23, 2015 | 10 | 2015 |
| Area implications of memory partitioning for high-level synthesis on FPGAs L Gallo, A Cilardo, D Thomas, S Bayliss, GA Constantinides 2014 24th International Conference on Field Programmable Logic and …, 2014 | 10 | 2014 |
| Vyasa: A high-performance vectorizing compiler for tensor convolutions on the Xilinx AI Engine P Chatarasi, S Neuendorffer, S Bayliss, K Vissers, V Sarkar 2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-10, 2020 | 4 | 2020 |
| Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies J Liu, J Wickerson, S Bayliss, GA Constantinides 2017 51st Asilomar Conference on Signals, Systems, and Computers, 126-130, 2017 | 3 | 2017 |
| Compiling higher order functional programs to composable digital hardware E Aguilar-Pelaez, S Bayliss, A Smith, F Winterstein, DR Ghica, D Thomas, ... 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 2 | 2014 |
| Analytical synthesis of bandwidth-efficient SDRAM address generators S Bayliss, GA Constantinides Microprocessors and Microsystems 36 (8), 665-675, 2012 | 2 | 2012 |
George ConstantinidesImperial College LondonEmail confirmado em ic.ac.uk
