Paul Molitor

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Bernd BeckerProfessor of Computer Science, University of FreiburgVerified email at informatik.uni-freiburg.de
Gerold JägerAssociate Professor in Mathematics, Umeå University, SwedenVerified email at umu.se
Rolf DrechslerProfessor at University of Bremen, Director DFKI Bremen, GermanyVerified email at uni-bremen.de
Boris GoldengorinProfessor of Operations Research, University of FloridaVerified email at hse.ru
Marcus PöckelmannMartin-Luther-Universität Halle-WittenbergVerified email at informatik.uni-halle.de
Sharad MalikProfessor of Electrical and Computer Engineering, Princeton UniversityVerified email at princeton.edu
Ivo GrosseProfessor of Bioinformatics, Martin Luther University Halle-WittenbergVerified email at informatik.uni-halle.de
Jens KeilwagenJulius Kuehn-InstituteVerified email at julius-kuehn.de
Michael KaufmannProfessor of Computer Science, Tübingen UniversityVerified email at uni-tuebingen.de
Goerschwin FeyHamburg University of TechnologyVerified email at tuhh.de
Schubert CharlotteProfessor for Ancient HistoryVerified email at uni-leipzig.de
Dorothea WagnerProfessor of Computer Science, Karlsruhe Institute of Technology (KIT)Verified email at kit.edu
Ricardo UsbeckFull Professor of AI and Explainability at Leuphana University LüneburgVerified email at leuphana.de
Natanael ArndtUniversität LeipzigVerified email at informatik.uni-leipzig.de

Paul Molitor

Martin Luther University Halle-Wittenberg, Institute for Computer Science

Verified email at informatik.uni-halle.de - Homepage

Computational Humanities / Text Collation Circuit Design / Formal Verification & Logic Synthesis


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Using Sifting for k-Layer Straightline Crossing Minimization C Matuszewski, R Schönfeld, P Molitor Graph Drawing: 7th International Symposium, GD’99 Štiřín Castle, Czech …, 1999	108	1999
BDD minimization using symmetries C Scholl, D Moller, P Molitor, R Drechsler IEEE transactions on computer-aided design of integrated circuits and …, 1999	93	1999
Equivalence checking of digital circuits: fundamentals, principles, methods P Molitor, J Mohnke Springer Science & Business Media, 2004	80	2004
Limits of using signatures for permutation independent Boolean comparison J Mohnke, P Molitor, S Malik Formal Methods in System Design 21, 167-191, 2002	73*	2002
Polynomial formal verification of multipliers M Keim, R Drechsler, B Becker, M Martin, P Molitor Formal Methods in System Design 22, 39-58, 2003	71*	2003
A pipelined architecture for partitioned DWT based lossy image compression using FPGA's J Ritter, P Molitor Proceedings of the 2001 ACM/SIGDA ninth international symposium on field …, 2001	67	2001
Technische Informatik B Becker, P Molitor Eine einführede Darstellung, Oldenbourg Verlag München Wien, Deuchland, 2008	56*	2008
Hierarchical design based on a calculus of nets B Becker, G Hotz, R Kolla, P Molitor, HG Osthof Proceedings of the 24th ACM/IEEE Design Automation Conference, 649-653, 1987	53*	1987
Exact algorithms and heuristics for the quadratic traveling salesman problem with an application in bioinformatics A Fischer, F Fischer, G Jäger, J Keilwagen, P Molitor, I Grosse Discrete Applied Mathematics 166, 97-114, 2014	50	2014
Algorithms and experimental study for the traveling salesman problem of second order G Jäger, P Molitor International Conference on Combinatorial Optimization and Applications …, 2008	45*	2008
Tolerances applied in combinatorial optimization B Goldengorin, G Jäger, P Molitor J. Comput. Sci 2 (9), 716-734, 2006	45	2006
Symmetry based variable ordering for ROBDDs D Möller, P Molitor, R Drechsler Logic and Architecture Synthesis: State-of-the-art and novel approaches, 70-81, 1995	44	1995
A survey on wiring P Molitor Elektronische Informationsverarbeitung und Kybernetik 27 (1), 3-19, 1991	40	1991
Minimizing ROBDD sizes of incompletely specified Boolean functions by exploiting strong symmetries C Scholl, S Melchior, G Hotz, P Molitor Proceedings European Design and Test Conference. ED & TC 97, 229-234, 1997	37	1997
Communication based FPGA synthesis for multi-output Boolean functions C Scholl, P Molitor Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 279-287, 1995	35	1995
Least upper bounds for the size of OBDDs using symmetry properties L Heinrich-Litan, P Molitor IEEE Transactions on computers 49 (4), 360-368, 2000	34*	2000
Einführung in den VLSI-Entwurf R Kolla, P Molitor, HG Osthof	30	1989
A Graphical System for Hierarchical Specifications and Checkups of VLSI Circuits’ G Hotz, B Becker, T Burch, P Molitor, D Kiel, R Kolla, U Sparmann, ... The Proceedings of the European Design Automation Conference, 174, 1990	28*	1990
On the generation of area-time optimal testable adders B Becker, R Drechsler, P Molitor IEEE transactions on computer-aided design of integrated circuits and …, 1995	27*	1995
SPIHT implemented in a XC4000 device J Ritter, G Fey, P Molitor The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002 …, 2002	25	2002

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