Subhasish Mitra
Subhasish Mitra
William E. Ayer Professor, Stanford University
Verified email at - Homepage
Cited by
Cited by
Carbon nanotube computer
MM Shulaker, G Hills, N Patil, H Wei, HY Chen, HSP Wong, S Mitra
Nature 501 (7468), 526-530, 2013
Robust system design with built-in soft-error resilience
S Mitra, N Seifert, M Zhang, Q Shi, KS Kim
Computer 38 (2), 43-52, 2005
The case for RAMClouds: scalable high-performance storage entirely in DRAM
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazières, ...
ACM SIGOPS Operating Systems Review 43 (4), 92-105, 2010
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
MM Shulaker, G Hills, RS Park, RT Howe, K Saraswat, HSP Wong, S Mitra
Nature 547 (7661), 74-78, 2017
Circuit failure prediction and its application to transistor aging
M Agarwal, BC Paul, M Zhang, S Mitra
25th IEEE VLSI Test Symposium (VTS'07), 277-286, 2007
Addressing failures in exascale computing
M Snir, RW Wisniewski, JA Abraham, SV Adve, S Bagchi, P Balaji, J Belak, ...
The International Journal of High Performance Computing Applications 28 (2 …, 2014
Which concurrent error detection scheme to choose?
S Mitra, EJ McCluskey
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
IFRA: Instruction footprint recording and analysis for post-silicon bug localization in processors
SB Park, S Mitra
Proceedings of the 45th annual Design Automation Conference, 373-378, 2008
ED/sup 4/I: error detection by diverse data and duplicated instructions
N Oh, S Mitra, EJ McCluskey
IEEE Transactions on Computers 51 (2), 180-199, 2002
Post-silicon bug localization in processors using instruction footprint recording and analysis (IFRA)
SB Park, T Hong, S Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
ERSA: Error resilient system architecture for probabilistic applications
L Leem, H Cho, J Bau, QA Jacobson, S Mitra
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
Quantitative evaluation of soft error injection techniques for robust system design
H Cho, S Mirkhani, CY Cher, JA Abraham, S Mitra
Proceedings of the 50th Annual Design Automation Conference, 1-10, 2013
Radiation-induced soft error rates of advanced CMOS bulk devices
N Seifert, P Slankard, M Kirsch, B Narasimham, V Zia, C Brookreson, A Vo, ...
2006 IEEE International Reliability Physics Symposium Proceedings, 217-225, 2006
Sequential element design with built-in soft error resilience
M Zhang, S Mitra, TM Mak, N Seifert, NJ Wang, Q Shi, KS Kim, ...
IEEE Transactions on very large scale integration (vlsi) systems 14 (12 …, 2006
Energy-efficient abundant-data computing: The N3XT 1,000 x
MMS Aly, M Gao, G Hills, CS Lee, G Pitner, MM Shulaker, TF Wu, ...
Computer 48 (12), 24-33, 2015
X-compact: An efficient response compaction technique
S Mitra, KS Kim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
X-compact: An efficient response compaction technique for test cost reduction
S Mitra, KS Kim
Proceedings. International Test Conference, 311-320, 2002
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
I Loi, S Mitra, TH Lee, S Fujita, L Benini
2008 IEEE/ACM International Conference on Computer-Aided Design, 598-602, 2008
Wafer-scale growth and transfer of aligned single-walled carbon nanotubes
N Patil, A Lin, ER Myers, K Ryu, A Badmaev, C Zhou, HSP Wong, S Mitra
IEEE Transactions on Nanotechnology 8 (4), 498-504, 2009
The case for RAMCloud
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazières, ...
Communications of the ACM 54 (7), 121-130, 2011
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