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Vikas Vij
Vikas Vij
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Characterization of asynchronous templates for integration into clocked CAD flows
KS Stevens, Y Xu, V Vij
2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 151-161, 2009
622009
A low power UART design based on asynchronous techniques
D Bhadra, VS Vij, KS Stevens
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
312013
The future of formal methods and GALS design
KS Stevens, D Gebhardt, J You, Y Xu, V Vij, S Das, K Desai
Electronic Notes in Theoretical Computer Science 245, 115-134, 2009
252009
Design of low energy, high performance synchronous and asynchronous 64-point FFT
W Lee, VS Vij, AR Thatcher, KS Stevens
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 242-247, 2013
232013
Sas: Source asynchronous signaling protocol for asynchronous handshake communication free from wire delay overhead
S Das, V Vij, KS Stevens
2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems …, 2013
112013
Interfacing synchronous and asynchronous domains for open core protocol
VS Vij, RP Gudla, KS Stevens
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
92014
Algorithms and methodology to design asynchronous circuits using synchronous CAD tools and flows
VS Vij
The University of Utah, 2013
82013
Automatic addition of reset in asynchronous sequential control circuits
VS Vij, KS Stevens
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013
52013
Timing path-driven cycle cutting for sequential controllers
W Lee, VS Vij, KS Stevens
ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (4 …, 2016
42016
Cycle cutting with timing path analysis
KS Stevens, V Vij
US Patent 8,365,116, 2013
42013
Cycle cutting with timing path analysis
KS Stevens, V Vij
US Patent App. 13/706,192, 2013
2013
Case Study: Multi-synchronous approaches to derive energy and architectural benefits in clocked peripherals
W Lee, V Vij, D Bhadra, K Stevens
2013
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