Steve Keckler
Steve Keckler
Vice President of Architecture Research, NVIDIA
Email confirmado em cs.utexas.edu - Página inicial
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Modeling the effect of technology trends on the soft error rate of combinational logic
P Shivakumar, M Kistler, SW Keckler, D Burger, L Alvisi
Proceedings International Conference on Dependable Systems and Networks, 389-398, 2002
19002002
Exascale computing study: Technology challenges in achieving exascale systems
P Kogge, K Bergman, S Borkar, D Campbell, W Carson, W Dally, ...
1372*2008
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
C Kim, D Burger, SW Keckler
ACM SIGPLAN Notices 37 (10), 211-222, 2002
9932002
Clock rate versus IPC: The end of the road for conventional microarchitectures
V Agarwal, MS Hrishikesh, SW Keckler, D Burger
Proceedings of the 27th annual international symposium on Computer …, 2000
9492000
Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture
K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, D Burger, ...
Computer Architecture, 2003. Proceedings. 30th Annual International …, 2003
7082003
GPUs and the future of parallel computing
SW Keckler, WJ Dally, B Khailany, M Garland, D Glasco
IEEE micro 31 (5), 7-17, 2011
6352011
Research challenges for on-chip interconnection networks
JD Owens, WJ Dally, R Ho, DN Jayasimha, SW Keckler, LS Peh
IEEE micro 27 (5), 96-108, 2007
5992007
Scnn: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017
5952017
Scaling to the End of Silicon with EDGE Architectures
D Burger, SW Keckler, KS McKinley, M Dahlin, LK John, C Lin, CR Moore, ...
Computer 37 (7), 44-55, 2004
4812004
A NUCA substrate for flexible CMP cache sharing
J Huh, C Kim, H Shafi, L Zhang, D Burger, SW Keckler
IEEE transactions on parallel and distributed systems 18 (8), 1028-1040, 2007
4722007
Regional congestion awareness for load balance in networks-on-chip
P Gratz, B Grot, SW Keckler
High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th …, 2008
4432008
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
MS Hrishikesh, D Burger, NP Jouppi, SW Keckler, KI Farkas, ...
ACM SIGARCH Computer Architecture News 30 (2), 14-24, 2002
3392002
Energy-efficient mechanisms for managing thread context in throughput processors
M Gebhart, DR Johnson, D Tarjan, SW Keckler, WJ Dally, E Lindholm, ...
2011 38th Annual International Symposium on Computer Architecture (ISCA …, 2011
2992011
Measuring experimental error in microprocessor simulation
R Desikan, D Burger, SW Keckler
Proceedings of the 28th annual international symposium on Computer …, 2001
2962001
The m-machine multicomputer
M Fillo, SW Keckler, WJ Dally, NP Carter, A Chang, Y Gurevich, WS Lee
International Journal of Parallel Programming 25 (3), 183-212, 1997
2921997
Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees
B Grot, J Hestness, SW Keckler, O Mutlu
2011 38th Annual International Symposium on Computer Architecture (ISCA …, 2011
2672011
Implementation and evaluation of on-chip network architectures
P Gratz, C Kim, R McDonald, SW Keckler, D Burger
Computer Design, 2006. ICCD 2006. International Conference on, 477-484, 2006
2432006
Exploring the design space of future CMPs
J Huh, D Burger, SW Keckler
Proceedings 2001 International Conference on Parallel Architectures and …, 2001
2432001
Express cube topologies for on-chip interconnects
B Grot, J Hestness, SW Keckler, O Mutlu
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
2392009
A design space evaluation of grid processor architectures
K Sankaralingam, R Nagarajan, D Burger, SW Keckler
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
237*2001
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