Michael C. Adler
Michael C. Adler
Email confirmado em intel.com
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HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing
M Pellauer, M Adler, M Kinsy, A Parashar, J Emer
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
1292011
Triggered instructions: A control paradigm for spatially-programmed architectures
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013
1092013
Leap scratchpads: automatic memory and cache management for reconfigurable logic
M Adler, KE Fleming, A Parashar, M Pellauer, J Emer
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
952011
Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
MC Adler, JS Yates Jr, DL Reese, PH Hohensee, SC Purcell
US Patent 6,978,462, 2005
622005
Software mechanism for reducing exceptions generated by speculatively scheduled instructions
R Cohn, MC Adler, PG Lowney
US Patent 5,901,308, 1999
621999
Leveraging latency-insensitivity to ease multiple FPGA design
KE Fleming, M Adler, M Pellauer, A Parashar, A Mithal, J Emer
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
612012
The LEAP FPGA operating system
K Fleming, M Adler
FPGAs for Software Programmers, 245-258, 2016
542016
Apparatus and method for speculatively executing instructions in a computer system
FX McKeen, MC Adler, JS Emer, RP Nix, DJ Sager, PG Lowney
US Patent 5,421,022, 1995
541995
Soft connections: Addressing the hardware-design modularity problem
M Pellauer, M Adler, D Chiou, J Emer
Proceedings of the 46th Annual Design Automation Conference, 276-281, 2009
482009
Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination
MC Adler, SO Hobbs, PG Lowney
US Patent 5,627,981, 1997
451997
Quick performance models quickly: Closely-coupled partitioned simulation on FPGAs
M Pellauer, M Vijayaraghavan, M Adler, J Emer
ISPASS 2008-IEEE International Symposium on Performance Analysis of Systems …, 2008
422008
Efficient spatial processing element control via triggered instructions
A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ...
IEEE Micro 34 (3), 120-137, 2014
402014
Executing distributed memory operations using processing elements connected by distributed channels
B Ahsan, MC Adler, NC Crago, JS Emer, A Jaleel, A Parashar, ...
US Patent 10,331,583, 2019
382019
Efficient control and communication paradigms for coarse-grained spatial architectures
M Pellauer, A Parashar, M Adler, B Ahsan, R Allmon, N Crago, K Fleming, ...
ACM Transactions on Computer Systems (TOCS) 33 (3), 1-32, 2015
382015
A-Ports: An efficient abstraction for cycle-accurate performance models on FPGAs
M Pellauer, M Vijayaraghavan, M Adler, J Emer
Proceedings of the 16th international ACM/SIGDA symposium on Field …, 2008
352008
Method and apparatus for propagating exception conditions of a computer system
FX McKeen, MC Adler, JS Emer, RP Nix, DJ Sager, PG Lowny
US Patent 5,428,807, 1995
321995
Mechanism for enforcing the correct order of instruction execution
FX McKeen, MC Adler, JS Emer, RP Nix, DJ Sager, PG Lowney
US Patent 5,420,990, 1995
311995
Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features
MC Adler, C Chou, NC Crago, K Fleming, KD Glossop, A Jaleel, ...
US Patent 10,387,319, 2019
292019
LEAP shared memories: Automating the construction of FPGA coherent memories
HJ Yang, K Fleming, M Adler, J Emer
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014
292014
Processors, methods, and systems for a configurable spatial accelerator with security, power reduction, and performace features
MC Adler, K Fleming, KD Glossop, SC Steely Jr
US Patent App. 15/640,542, 2019
272019
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