Follow
Nur Touba
Nur Touba
Professor of Electrical and Computer Engineering, University of Texas at Austin
Verified email at ece.utexas.edu - Homepage
Title
Cited by
Cited by
Year
Survey of test vector compression techniques
NA Touba
IEEE Design & test of computers 23 (4), 294-303, 2006
5312006
Static compaction techniques to control scan vector power dissipation
R Sankaralingam, RR Oruganti, NA Touba
Proceedings 18th IEEE VLSI Test Symposium, 35-40, 2000
4672000
Scan vector compression/decompression using statistical coding
A Jas, J Ghosh-Dastidar, NA Touba
Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 114-120, 1999
4071999
Test vector decompression via cyclical scan chains and its application to testing core-based designs
A Jas, NA Touba
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
3841998
System-on-Chip Test Architectures: Nanometer Design for Testability (Systems on Silicon)
LT Wang, CE Stroud, NA Touba
Morgan Kaufmann, 2009
367*2009
Cost-effective approach for reducing soft error failure rate in logic circuits
K Mohanram, NA Touba
ITC 1, 893-901, 2003
3652003
An efficient test vector compression scheme using selective Huffman coding
A Jas, J Ghosh-Dastidar, ME Ng, NA Touba
IEEE transactions on computer-aided design of integrated circuits and …, 2003
3652003
Test vector encoding using partial LFSR reseeding
CV Krishna, A Jas, NA Touba
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 885-893, 2001
2972001
Altering a pseudo-random bit sequence for scan-based BIST
NA Touba, EJ McCluskey
Proceedings International Test Conference 1996. Test and Design Validity …, 1996
2531996
Synthesis of circuits with low-cost concurrent error detection based on Bose-Lin codes
D Das, NA Touba
Journal of Electronic Testing 15 (1), 145-155, 1999
2341999
Reducing test data volume using LFSR reseeding with seed compression
CV Krishna, NA Touba
Proceedings. International Test Conference, 321-330, 2002
2332002
Logic synthesis of multilevel circuits with concurrent error detection
NA Touba, EJ McCluskey
IEEE transactions on computer-aided design of integrated circuits and …, 1997
2271997
Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code
A Dutta, NA Touba
25th IEEE VLSI Test Symposium (VTS'07), 349-354, 2007
2262007
Reducing power dissipation during test using scan chain disable
R Sankaralingam, B Pouya, NA Touba
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 319-324, 2001
1982001
Reducing test data volume using external/LBIST hybrid test patterns
D Das, NA Touba
Proceedings International Test Conference 2000 (IEEE Cat. No. 00CH37159 …, 2000
1592000
Weight-based codes and their application to concurrent error detection of multilevel circuits
D Das, NA Touba
Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 370-376, 1999
1591999
Test point insertion based on path tracing
NA Touba, EJ McCluskey
Proceedings of 14th VLSI Test Symposium, 2-8, 1996
1531996
Controlling peak power during scan testing
R Sankaralingam, NA Touba
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 153-159, 2002
1402002
Virtual scan chains: A means for reducing scan length in cores
A Jas, B Pouya, NA Touba
Proceedings 18th IEEE VLSI Test Symposium, 73-78, 2000
1372000
Test data compression using dictionaries with selective entries and fixed-length indices
L Li, K Chakrabarty, NA Touba
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003
1302003
The system can't perform the operation now. Try again later.
Articles 1–20