CEA-LETI, Minatec Campus
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A CMOS silicon spin qubit
R Maurand, X Jehl, D Kotekar-Patil, A Corna, H Bohuslavskyi, R Laviéville, ...
Nature communications 7 (1), 1-6, 2016
Planar Fully depleted SOI technology: A Powerful architecture for the 20nm node and beyond
O Faynot, F Andrieu, O Weber, C Fenouillet-Béranger, P Perreau, ...
2010 International Electron Devices Meeting, 3.2. 1-3.2. 4, 2010
Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm
S Barraud, M Berthome, R Coquand, M Cassé, T Ernst, MP Samson, ...
IEEE Electron Device Letters 33 (9), 1225-1227, 2012
Performance of omega-shaped-gate silicon nanowire MOSFET with diameter down to 8 nm
S Barraud, R Coquand, M Casse, M Koyama, JM Hartmann, ...
IEEE Electron Device Letters 33 (11), 1526-1528, 2012
Probing the limits of gate-based charge sensing
MF Gonzalez-Zalba, S Barraud, AJ Ferguson, AC Betz
Nature communications 6 (1), 1-8, 2015
Revisited parameter extraction methodology for electrical characterization of junctionless transistors
DY Jeon, SJ Park, M Mouis, M Berthomé, S Barraud, GT Kim, G Ghibaudo
Solid-State Electronics 90, 86-93, 2013
Few-electron edge-state quantum dots in a silicon nanowire field-effect transistor
B Voisin, VH Nguyen, J Renard, X Jehl, S Barraud, F Triozon, M Vinet, ...
Nano letters 14 (4), 2094-2098, 2014
Nanoscaled MOSFET Transistors on Strained Si, SiGe, Ge Layers: Some Integration and Electrical Properties Features
TP Ernst, F Andrieu, O Weber, JM Hartmann, C Dupre, O Faynot, ...
ECS Transactions 3 (7), 947, 2006
Effect of discrete impurities on electron transport in ultrashort MOSFET using 3D MC simulation
P Dollfus, A Bournel, S Galdin, S Barraud, P Hesto
IEEE Transactions on Electron Devices 51 (5), 749-756, 2004
Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET
B Voisin, R Maurand, S Barraud, M Vinet, X Jehl, M Sanquer, J Renard, ...
Nano letters 16 (1), 88-92, 2016
Strain-induced performance enhancement of trigate and omega-gate nanowire FETs scaled down to 10-nm width
R Coquand, M Casse, S Barraud, D Cooper, V Maffini-Alvaro, ...
IEEE Transactions on Electron Devices 60 (2), 727-732, 2012
Low-temperature electrical characterization of junctionless transistors
DY Jeon, SJ Park, M Mouis, S Barraud, GT Kim, G Ghibaudo
Solid-State Electronics 80, 135-141, 2013
Electrical Spin Driving by -Matrix Modulation in Spin-Orbit Qubits
A Crippa, R Maurand, L Bourdet, D Kotekar-Patil, A Amisse, X Jehl, ...
Physical review letters 120 (13), 137702, 2018
Vertically stacked-nanowires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
S Barraud, V Lapras, MP Samson, L Gaben, L Grenouillet, ...
2016 IEEE International Electron Devices Meeting (IEDM), 17.6. 1-17.6. 4, 2016
Performance and design considerations for gate-all-around stacked-NanoWires FETs
S Barraud, V Lapras, B Previtali, MP Samson, J Lacord, S Martinie, ...
2017 IEEE international electron devices meeting (IEDM), 29.2. 1-29.2. 4, 2017
Gate-based high fidelity spin readout in a CMOS device
M Urdampilleta, DJ Niegemann, E Chanrion, B Jadot, C Spence, ...
Nature nanotechnology 14 (8), 737-741, 2019
Electrically driven electron spin resonance mediated by spin–valley–orbit coupling in a silicon quantum dot
A Corna, L Bourdet, R Maurand, A Crippa, D Kotekar-Patil, ...
npj quantum information 4 (1), 1-7, 2018
3D analysis of advanced nano-devices using electron and atom probe tomography
A Grenier, S Duguay, JP Barnes, R Serra, G Haberfehlner, D Cooper, ...
Ultramicroscopy 136, 185-192, 2014
Gate-sensing coherent charge oscillations in a silicon field-effect transistor
MF Gonzalez-Zalba, SN Shevchenko, S Barraud, JR Johansson, ...
Nano letters 16 (3), 1614-1619, 2016
Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width
R Coquand, S Barraud, M Cassé, P Leroux, C Vizioz, C Comboroure, ...
Solid-State Electronics 88, 32-36, 2013
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