Constantinos Efstathiou
Constantinos Efstathiou
Professor, Dept. of Informatics and Computer Engineering, University of West Attica
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TítuloCitado porAno
Diminished-one modulo 2/sup n/+ 1 adder design
HT Vergos, C Efstathiou, D Nikolos
IEEE Transactions on Computers 51 (12), 1389-1399, 2002
1792002
High-speed parallel-prefix module 2/sup n/-1 adders
L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos
IEEE Transactions on Computers 49 (7), 673-680, 2000
1742000
Fast parallel-prefix modulo 2/sup n/+ 1 adders
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (9), 1211-1216, 2004
1172004
Modified Booth modulo 2/sup n/-1 multipliers
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 53 (3), 370-374, 2004
842004
Area-time efficient modulo 2/sup n/-1 adder design
C Efstathiou, D Nikolos, J Kalamatianos
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1994
831994
Efficient diminished-1 modulo 2/sup n/+ 1 multipliers
C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos
IEEE Transactions on Computers 54 (4), 491-496, 2005
822005
Modulo 2/sup n//spl plusmn/1 adder design using select-prefix blocks
C Efstathiou, HT Vergos, D Nikolos
IEEE Transactions on Computers 52 (11), 1399-1406, 2003
762003
Design of efficient modulo 2n+ 1 multipliers
HT Vergos, C Efstathiou
IET Computers & Digital Techniques 1 (1), 49-57, 2007
722007
A Unifying Approach for Weighted and Diminished-1 Modulo Addition
HT Vergos, C Efstathiou
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 1041-1045, 2008
572008
An optimized modified booth recoder for efficient design of the add-multiply operator
K Tsoumanis, S Xydis, C Efstathiou, N Moschopoulos, K Pekmestzi
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1133-1143, 2014
552014
New architectures for modulo 2n-1 adders
G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou
2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005
352005
Efficient modulo 2n+ 1 adder architectures
HT Vergos, C Efstathiou
Integration 42 (2), 149-157, 2009
342009
Handling zero in diminished-one modulo 2 n + 1 adders
C Efstathiou, HT Vergos, D Nikolos
International journal of electronics 90 (2), 133-144, 2003
332003
New high-speed multioutput carry look-ahead adders
C Efstathiou, Z Owda, Y Tsiatouhas
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (10), 667-671, 2013
312013
An efficient TSC 1-out-of-3 code checker
AM Paschalis, C Efstathiou, C Halatsis
IEEE transactions on computers 39 (3), 407-411, 1990
301990
A concurrent BIST architecture based on monitoring square windows
I Voyiatzis, T Haniotakis, C Efstathiou, H Antonopoulou
5th International Conference on Design & Technology of Integrated Systems in …, 2010
232010
A family of parallel-prefix modulo 2/sup n/-1 adders
G Dimitrakopoulos, HT Vergos, D Nikolos, C Efstathiou
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
192003
Modular realization of totally self-checking checkers for m-out-of-n codes
C Efstathiou, C Halatsis
Proc. Int. Symp. FaultTolerant Computing, 154-161, 1983
191983
Diminished-1 modulo 2n+ 1 squarer design
HT Vergos, C Efstathiou
IEE Proceedings-Computers and Digital Techniques 152 (5), 561-566, 2005
182005
Noise properties of degenerate dual pump phase sensitive amplifiers
A Bogris, D Syvridis, C Efstathiou
Journal of Lightwave Technology 28 (8), 1209-1217, 2010
172010
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