Nuno Horta
Nuno Horta
Associate Professor, Instituto de Telecomunicações, Instituto Superior Técnico, U Lisboa
Verified email at lx.it.pt - Homepage
TitleCited byYear
Analog circuits optimization based on evolutionary computation techniques
M Barros, J Guilherme, N Horta
Integration 43 (1), 136-155, 2010
952010
Applying a GA kernel on optimizing technical analysis rules for stock picking and portfolio composition
A Gorgulho, R Neves, N Horta
Expert systems with Applications 38 (11), 14072-14085, 2011
902011
Analog circuits and systems optimization based on evolutionary computation techniques
MFM Barros, JMC Guilherme, NCG Horta
Springer, 2010
892010
LAYGEN II—Automatic layout generation of analog integrated circuits
R Martins, N Lourenco, N Horta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
742013
A multi-objective model for scheduling of short-term incentive-based demand response programs offered by electricity retailers
MAF Ghazvini, J Soares, N Horta, R Neves, R Castro, Z Vale
Applied energy 151, 102-118, 2015
692015
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation
N Lourenço, N Horta
Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012
462012
AIDA: Automated analog IC design flow from circuit level to layout
R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
432012
A multi-objective routing algorithm for wireless multimedia sensor networks
N Magaia, N Horta, R Neves, PR Pereira, M Correia
Applied Soft Computing 30, 104-112, 2015
412015
Reconfigurable multi-mode sigma–delta modulator for 4G mobile terminals
A Silva, J Guilherme, N Horta
Integration, the VLSI Journal 42 (1), 34-46, 2009
402009
Company event popularity for financial markets using Twitter and sentiment analysis
M Daniel, RF Neves, N Horta
Expert Systems with Applications 71, 111-124, 2017
382017
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction
N Lourenço, R Martins, N Horta
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
322015
Floorplan-aware analog IC sizing and optimization based on topological constraints
N Lourenço, A Canelas, R Póvoa, R Martins, N Horta
Integration, the VLSI journal 48, 183-197, 2015
322015
A hybrid approach to portfolio composition based on fundamental and technical indicators
A Silva, R Neves, N Horta
Expert Systems with Applications 42 (4), 2036-2048, 2015
302015
AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation
R Martins, N Lourenço, A Canelas, R Póvoa, N Horta
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
292015
A SAX-GA approach to evolve investment strategies on financial markets based on pattern discovery techniques
AN Canelas, R Neves, N Horta
Expert Systems with Applications 40 (5), 1579-1590, 2013
272013
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
N Lourenço, R Martins, A Canelas, R Póvoa, N Horta
Integration 55, 316-329, 2016
242016
GA-SVM feasibility model and optimization kernel applied to analog IC design automation
M Barros, J Guilherme, N Horta
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 469-472, 2007
242007
LAYGEN-automatic layout generation of analog ICs from hierarchical template descriptions
N Lourenço, M Vianello, J Guilherme, N Horta
2006 Ph. D. Research in Microelectronics and Electronics, 213-216, 2006
242006
Algorithm-driven synthesis of data conversion architectures
NC Horta, JE Franca
IEEE transactions on computer-aided design of integrated circuits and …, 1997
241997
Electromigration-aware analog Router with multilayer multiport terminal structures
R Martins, N Lourenco, A Canelas, N Horta
Integration, the VLSI Journal 47 (4), 532-547, 2014
232014
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Articles 1–20