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Eric Cheng
Eric Cheng
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Title
Cited by
Cited by
Year
CLEAR: Cross-layer exploration for architecting resilience: Combining hardware and software techniques to tolerate soft errors in processor cores
E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ...
Design Automation Conference (DAC), 2016 53nd ACM/EDAC/IEEE, 1-6, 2016
1012016
The resilience wall: Cross-layer solution strategies
S Mitra, P Bose, E Cheng, CY Cher, H Cho, R Joshi, YM Kim, CR Lefurgy, ...
Proceedings of Technical Program-2014 International Symposium on VLSI …, 2014
472014
Self-repair of uncore components in robust system-on-chips: An opensparc t2 case study
Y Li, E Cheng, S Makar, S Mitra
2013 IEEE International Test Conference (ITC), 1-10, 2013
302013
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)
E Cheng, S Mirkhani, LG Szafaryn, CY Cher, H Cho, K Skadron, MR Stan, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
262017
System-level effects of soft errors in uncore components
H Cho, E Cheng, T Shepherd, CY Cher, S Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
232017
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques
D Mueller-Gritschneder, M Dittrich, J Weinzierl, E Cheng, S Mitra, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 609-612, 2018
112018
Very Low Voltage (VLV) Design
R Bertran, P Bose, D Brooks, J Burns, A Buyuktosunoglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 601-604, 2017
112017
Cross-layer resilience to tolerate hardware errors in digital systems
E Cheng
Stanford University, 2018
62018
Cross-layer resilience in low-voltage digital systems: key insights
E Cheng, J Abraham, P Bose, A Buyuktosunoglu, K Campbell, D Chen, ...
2017 IEEE International Conference on Computer Design (ICCD), 593-596, 2017
62017
Self-repair of Uncore components in robust systems-on-chips
Y Li, E Cheng, S Makar, S Mitra
SELSE, 2013
32013
Cross-Layer Resilience Against Soft Errors: Key Insights
D Mueller-Gritschneder, E Cheng, U Sharif, V Kleeberger, P Bose, S Mitra, ...
Dependable Embedded Systems, 249-275, 2021
2021
Cross-layer resilience
E Cheng, S Mitra
Cross-Layer Reliability of Computing Systems, 113, 2020
2020
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