Dr. Veeresh Deshpande
Dr. Veeresh Deshpande
Email confirmado em helmholtz-berlin.de
Citado por
Citado por
Confined epitaxial lateral overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates
L Czornomaz, E Uccelli, M Sousa, V Deshpande, V Djara, D Caimi, ...
2015 Symposium on VLSI Technology (VLSI Technology), T172-T173, 2015
Synthesis of bismuth oxide nanoparticles at 100 C
MM Patil, VV Deshpande, SR Dhage, V Ravi
Materials letters 59 (19-20), 2523-2525, 2005
A tunable, dual mode field-effect or single electron transistor
B Roche, B Voisin, X Jehl, R Wacquez, M Sanquer, M Vinet, ...
Applied Physics Letters 100 (3), 032107, 2012
Advanced 3D monolithic hybrid CMOS with sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs
V Deshpande, V Djara, E O'Connor, P Hashemi, K Balakrishnan, M Sousa, ...
2015 IEEE International Electron Devices Meeting (IEDM), 8.8. 1-8.8. 4, 2015
Individually packaged body fluid absorbent article
A Suga
US Patent App. 10/256,092, 2003
CMOS-Compatible Replacement Metal Gate InGaAs-OI FinFET WithatV andnA/
V Djara, V Deshpande, M Sousa, D Caimi, L Czornomaz, J Fompeyrine
IEEE Electron Device Letters 37 (2), 169-172, 2016
Low voltage varistors based on CeO2
VV Deshpande, MM Patil, V Ravi
Ceramics international 32 (1), 85-87, 2006
An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch
V Djara, V Deshpande, E Uccelli, N Daix, D Caimi, C Rossel, M Sousa, ...
2015 Symposium on VLSI Technology (VLSI Technology), T176-T177, 2015
Scaling of trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to single electron transistor
V Deshpande, S Barraud, X Jehl, R Wacquez, M Vinet, R Coquand, ...
Solid-state electronics 84, 179-184, 2013
A coprecipitation technique to prepare ZnNb2O6 powders
VV Deshpande, MM Patil, SC Navale, V Ravi
Bulletin of Materials Science 28 (3), 205-207, 2005
First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes
L Czornomaz, V Djara, V Deshpande, E O'Connor, M Sousa, D Caimi, ...
2016 IEEE Symposium on VLSI Technology, 1-2, 2016
Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm
R Wacquez, M Vinet, M Pierre, B Roche, X Jehl, O Cueto, J Verduijn, ...
2010 Symposium on VLSI Technology, 193-194, 2010
First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ...
2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018
A scaled replacement metal gate InGaAs-on-Insulator n-FinFET on Si with record performance
H Hahn, V Deshpande, E Caruso, S Sant, E O'Connor, Y Baumgartner, ...
2017 IEEE International Electron Devices Meeting (IEDM), 17.5. 1-17.5. 4, 2017
Three-dimensional monolithic integration of III–V and Si (Ge) FETs for hybrid CMOS and beyond
V Deshpande, V Djara, E O’Connor, P Hashemi, T Morf, K Balakrishnan, ...
Japanese Journal of Applied Physics 56 (4S), 04CA05, 2017
Device and method for minimizing restenosis after angioplasty treatment
W Neuberger
US Patent 6,984,229, 2006
A coprecipitation technique to prepare Mg4Nb2O9 powders
VV Deshpande, MM Patil, V Ravi
Ceramics international 32 (3), 353-355, 2006
3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability
A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ...
IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018
Ambipolar quantum dots in undoped silicon fin field-effect transistors
AV Kuhlmann, V Deshpande, LC Camenzind, DM Zumbühl, A Fuhrer
Applied Physics Letters 113 (12), 122107, 2018
First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts
V Deshpande, H Hahn, E O'Connor, Y Baumgartner, M Sousa, D Caimi, ...
2017 Symposium on VLSI Technology, T74-T75, 2017
O sistema não pode efectuar a operação agora. Tente novamente mais tarde.
Artigos 1–20