Víctor Viñals-Yúfera
Víctor Viñals-Yúfera
Verified email at unizar.es - Homepage
Title
Cited by
Cited by
Year
Delaying physical register allocation through virtual-physical registers
T Monreal, A González, M Valero, J González, V Vinals
MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on …, 1999
1251999
The reuse cache: Downsizing the shared last-level cache
J Albericio, P Ibáñez, V Viñals, JM Llabería
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
622013
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors
MJ Garzarán, M Prvulovic, JM Llabería, V Viñals, L Rauchwerger, ...
ACM Transactions on Architecture and Code Optimization (TACO) 2 (3), 247-279, 2005
602005
Hardware schemes for early register release
T Monreal, V Viñals, A González, M Valero
Proceedings International Conference on Parallel Processing, 5-13, 2002
582002
Store buffer design in first-level multibanked data caches
EF Torres, P Ibánez, V Viñals, JM Llabería
32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005
502005
Tradeoffs in buffering memory state for thread-level speculation in multiprocessors
MJ Garzaran, M Prvulovic, JM Llaberia, V Vinals, L Rauchwerger, ...
The Ninth International Symposium on High-Performance Computer Architecture …, 2003
482003
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems
LC Aparicio, J Segarra, C Rodríguez, V Viñals
Journal of Systems Architecture 57 (7), 695-706, 2011
362011
Late allocation and early release of physical registers
T Monreal, V Vinals, J González, A González, M Valero
IEEE Transactions on Computers 53 (10), 1244-1259, 2004
332004
Dynamic register renaming through virtual-physical registers
T Monreal, A González, M Valero, J González, V Viñals
Journal of Instruction Level Parallelism, 2000
282000
Exploiting reuse locality on inclusive shared last-level caches
J Albericio, P Ibáñez, V Viñals, JM Llabería
ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-19, 2013
262013
Multi-level adaptive prefetching based on performance gradient tracking
LM Ramos, JL Briz, PE Ibáñez, V Viñals
Journal of Instruction-Level Parallelism 13, 1-14, 2011
262011
LP-NUCA: Networks-in-cache for high-performance low-power embedded processors
DS Gracia, G Dimitrakopoulos, TM Arnal, MGH Katevenis, VV Yúfera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (8 …, 2011
242011
Contrasting laser power requirements of wavelength-routed optical NoC topologies subject to the floorplanning, placement, and routing constraints of a 3-D-stacked system
M Ortín-Obón, M Tala, L Ramini, V Viñals-Yufera, D Bertozzi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (7 …, 2017
222017
Combining prefetch with instruction cache locking in multitasking real-time systems
LC Aparicio, J Segarra, C Rodriguez, V Vinals
2010 IEEE 16th International Conference on Embedded and Real-Time Computing …, 2010
192010
Capturing the sensitivity of optical network quality metrics to its network interface parameters
M Ortín‐Obón, L Ramini, V Viñals, D Bertozzi
Concurrency and Computation: Practice and Experience 26 (15), 2504-2517, 2014
172014
Avoiding the WCET overestimation on LRU instruction cache
LC Aparicio, J Segarra, C Rodríguez, JL Villarroel, V Viñals
2008 14th IEEE International Conference on Embedded and Real-Time Computing …, 2008
162008
TDR-LAB 2.0 Improved TDR Software for soil water content and electrical conductivity measurements
E Fatás, J Vicente, B Latorre, F Lera, V Viñals, MV López, N Blanco, ...
Procedia Environmental Sciences 19, 474-483, 2013
152013
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors
M Ortín-Obón, D Suárez-Gracia, M Villarroya-Gaudó, C Izu, ...
Microprocessors and Microsystems 42, 24-36, 2016
142016
Using software logging to support multiversion buffering in thread-level speculation
MJ Garzarán, M Prvulovic, V Viñals, JM Llabería, L Rauchwerger, ...
2003 12th International Conference on Parallel Architectures and Compilation …, 2003
142003
Characterization and improvement of load/store cache-based prefetching
P Ibáñez, V Viñals, JL Briz, MJ Garzarán
Proceedings of the 12th international conference on Supercomputing, 369-376, 1998
141998
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