Rouwaida Kanj
Title
Cited by
Cited by
Year
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events
R Kanj, R Joshi, S Nassif
2006 43rd ACM/IEEE Design Automation Conference, 69-72, 2006
3832006
Low cost arduino/android-based energy-efficient home automation system with smart task scheduling
K Baraka, M Ghobril, S Malek, R Kanj, A Kayssi
2013 Fifth international conference on computational intelligence …, 2013
1612013
Document retrieval using internal dictionary-hierarchies to adjust per-subject match results
AE Gattiker, FH Gebara, AN Hylick, RN Kanj
US Patent 9,235,638, 2016
1532016
Method and computer program for efficient cell failure rate estimation in cell arrays
RV Joshi, RN Kanj, SR Nassif
US Patent 7,380,225, 2008
1272008
Methodology for correlated memory fail estimations
RV Joshi, RN Kanj, SR Nassif
US Patent 8,214,190, 2012
1092012
In-situ design method and system for improved memory yield
RV Joshi, R Kanj
US Patent 8,170,857, 2012
1032012
Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data
F Wang, P Cachecho, W Zhang, S Sun, X Li, R Kanj, C Gu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
782015
The impact of aging effects and manufacturing variation on SRAM soft-error rate
EH Cannon, AJ KleinOsowski, R Kanj, DD Reinhardt, RV Joshi
IEEE Transactions on Device and Materials Reliability 8 (1), 145-152, 2008
692008
Cross layer error exploitation for aggressive voltage scaling
AK Djahromi, AM Eltawil, FJ Kurdahi, R Kanj
8th International Symposium on Quality Electronic Design (ISQED'07), 192-197, 2007
582007
A novel column-decoupled 8T cell for low-power differential and domino-based SRAM design
RV Joshi, R Kanj, V Ramadurai
IEEE transactions on very large scale integration (VLSI) systems 19 (5), 869-882, 2010
512010
System-level SRAM yield enhancement
FJ Kurdahi, AM Eltawil, YH Park, RN Kanj, SR Nassif
7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-184, 2006
382006
Feature extraction that supports progressively refined search and classification of patterns in a semiconductor layout
DL DeMaris, RN Kanj, DN Maynard, MD Monkowski
US Patent App. 11/765,473, 2008
352008
A disturb decoupled column select 8T SRAM cell
V Ramadurai, R Joshi, R Kanj
2007 IEEE Custom Integrated Circuits Conference, 25-28, 2007
312007
FinFET SRAM design
R Joshi, K Kim, R Kanj
Nanoelectronic Circuit Design, 55-95, 2011
292011
A thermal and process variation aware MTJ switching model and its applications in soft error analysis
P Wang, E Eken, W Zhang, R Joshi, R Kanj, Y Chen
More than Moore Technologies for Next Generation Computer Design, 101-125, 2015
282015
Strained SOI FinFET SRAM Design
P Kerber, R Kanj, RV Joshi
IEEE electron device letters 34 (7), 876-878, 2013
222013
Technology computer-aided design (TCAD)-based virtual fabrication
RV Joshi, RN Kanj, K Kim
US Patent 8,515,724, 2013
212013
Systems and methods for memory device precharging
JW Dawson, RV Joshi, N Jungmann, E Kachir, RN Kanj, E Nir, DW Plass
US Patent 8,472,271, 2013
212013
Statistical exploration of the dual supply voltage space of a 65nm PD/SOI CMOS SRAM cell
R Joshi, R Kanj, S Nassif, D Plass, Y Chan
2006 European Solid-State Device Research Conference, 315-318, 2006
212006
Broken-spheres methodology for improved failure probability analysis in multi-fail regions
RV Joshi, RN Kanj, Z Li, SR Nassif
US Patent 8,365,118, 2013
162013
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