| High—Level Synthesis: Introduction to Chip and System Design DD Gajski, ND Dutt, ACH Wu, SYL Lin Springer Science & Business Media, 2012 | 2023 | 2012 |
| EXPRESSION: A language for architecture exploration through compiler/simulator retargetability A Halambi, P Grun, V Ganesh, A Khare, N Dutt, A Nicolau Design, Automation, and Test in Europe, 31-45, 2008 | 571 | 2008 |
| Data and memory optimization techniques for embedded systems PR Panda, F Catthoor, ND Dutt, K Danckaert, E Brockmeyer, C Kulkarni, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 6 (2 …, 2001 | 533 | 2001 |
| SPARK: A high-level synthesis framework for applying parallelizing compiler transformations S Gupta, N Dutt, R Gupta, A Nicolau 16th International Conference on VLSI Design, 2003. Proceedings., 461-466, 2003 | 487 | 2003 |
| On-chip communication architectures: system on chip interconnect S Pasricha, N Dutt Morgan Kaufmann, 2010 | 448 | 2010 |
| Efficient utilization of scratch-pad memory in embedded processor applications PR Panda, ND Dutt, A Nicolau Proceedings European Design and Test Conference. ED & TC 97, 7-11, 1997 | 396 | 1997 |
| Memory issues in embedded systems-on-chip: optimizations and exploration PR Panda, ND Dutt, A Nicolau Springer Science & Business Media, 1999 | 348 | 1999 |
| On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems PR Panda, ND Dutt, A Nicolau ACM Transactions on Design Automation of Electronic Systems (TODAES) 5 (3 …, 2000 | 320 | 2000 |
| A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors JM Nageswaran, N Dutt, JL Krichmar, A Nicolau, AV Veidenbaum Neural networks 22 (5-6), 791-800, 2009 | 263 | 2009 |
| Silicon compilation DD Gajski, ND Dutt, BM Pangrle | 238 | 1987 |
| Partitioned register files for VLIWs: A preliminary analysis of tradeoffs A Capitanio, N Dutt, A Nicolau ACM SIGMICRO Newsletter 23 (1-2), 292-300, 1992 | 228 | 1992 |
| Reliable on-chip systems in the nano-era: Lessons learnt and future trends J Henkel, L Bauer, N Dutt, P Gupta, S Nassif, M Shafique, M Tahoori, ... 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 1-10, 2013 | 226 | 2013 |
| Profile-based dynamic voltage scheduling using program checkpoints A Azevedo, I Issenin, R Cornea, R Gupta, N Dutt, A Veidenbaum, ... Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 223 | 2002 |
| SPARK: a parallelizing approach to the high-level synthesis of digital circuits S Gupta, R Gupta, ND Dutt, A Nicolau Springer Science & Business Media, 2007 | 210 | 2007 |
| Instruction set compiled simulation: A technique for fast and flexible instruction set simulation M Reshadi, P Mishra, N Dutt Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451 …, 2003 | 187 | 2003 |
| Integrated power management for video streaming to mobile handheld devices S Mohapatra, R Cornea, N Dutt, A Nicolau, N Venkatasubramanian Proceedings of the eleventh ACM international conference on Multimedia, 582-591, 2003 | 177 | 2003 |
| Underdesigned and opportunistic computing in presence of hardware variability P Gupta, Y Agarwal, L Dolecek, N Dutt, RK Gupta, R Kumar, S Mitra, ... IEEE Transactions on Computer-Aided Design of integrated circuits and …, 2012 | 167 | 2012 |
| Extending the transaction level modeling approach for fast communication architecture exploration S Pasricha, N Dutt, M Ben-Romdhane Proceedings of the 41st annual Design Automation Conference, 113-118, 2004 | 164 | 2004 |
| Processor description languages P Mishra, N Dutt Elsevier, 2011 | 156 | 2011 |
| Fast configurable-cache tuning with a unified second-level cache A Gordon-Ross, F Vahid, ND Dutt IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (1), 80-91, 2008 | 151 | 2008 |
