LAYGEN II—automatic layout generation of analog integrated circuits R Martins, N Lourenco, N Horta
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2013
77 2013 AIDA: Automated analog IC design flow from circuit level to layout R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta
2012 International Conference on Synthesis, Modeling, Analysis and …, 2012
43 2012 AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation N Lourenço, R Martins, A Canelas, R Povoa, N Horta
Integration 55, 316-329, 2016
35 * 2016 AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation R Martins, N Lourenço, A Canelas, R Póvoa, N Horta
2015 International Conference on Synthesis, Modeling, Analysis and …, 2015
32 2015 Floorplan-aware analog IC sizing and optimization based on topological constraints N Lourenço, A Canelas, R Póvoa, R Martins, N Horta
Integration 48, 183-197, 2015
32 2015 Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction N Lourenço, R Martins, N Horta
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
31 2015 Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates R Martins, N Lourenço, N Horta
Expert Systems with Applications 42 (23), 9137-9151, 2015
28 2015 Automatic analog IC sizing and optimization constrained with PVT corners and layout effects N Lourenço, R Martins, N Horta
Springer International Publishing, 2017
25 2017 Electromigration-aware analog Router with multilayer multiport terminal structures R Martins, N Lourenco, A Canelas, N Horta
Integration 47 (4), 532-547, 2014
23 2014 Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop R Martins, N Lourenço, F Passos, R Póvoa, A Canelas, E Roca, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
20 2018 Electronic design automation of analog ICs combining gradient models with multi-objective evolutionary algorithms FAE Rocha, RMF Martins, NCC Lourenço, NCG Horta
Springer Science & Business Media, 2013
20 * 2013 Analog Integrated Circuit Design Automation R Martins, N Lourenço, N Horta
Springer, 2017
17 2017 LC-VCO automatic synthesis using multi-objective evolutionary techniques R Póvoa, R Lourenço, N Lourenço, A Canelas, R Martins, N Horta
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 293-296, 2014
17 2014 Electromigration-aware and IR-drop avoidance routing in analog multiport terminal structures R Martins, N Lourenço, A Canelas, N Horta
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
15 2014 Laygen ii: automatic analog ics layout generator based on a template approach R Martins, N Lourenço, N Horta
Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012
15 2012 Current-flow and current-density-aware multi-objective optimization of analog IC placement R Martins, R Povoa, N Lourenco, N Horta
Integration 55, 295-306, 2016
14 2016 Using artificial neural networks for analog integrated circuit design automation JPS Rosa, DJD Guerra, NCG Horta, RMF Martins, NCC Lourenço
Springer Nature, 2019
13 * 2019 Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications R Martins, N Lourenço, N Horta, J Yin, PI Mak, RP Martins
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018
13 2018 FUZYE: A Fuzzy A Canelas, R Póvoa, R Martins, N Lourenço, J Guilherme, JP Carvalho, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
11 2018 Single-stage OTA biased by voltage-combiners with enhanced performance using current starving R Povoa, N Lourenço, R Martins, A Canelas, N Horta, J Goes
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1599-1603, 2017
11 2017 
Nuno LourençoInstituto de Telecomunicações (IT)Email confirmado em lx.it.pt
