| LAYGEN II—automatic layout generation of analog integrated circuits R Martins, N Lourenco, N Horta Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2013 | 74 | 2013 |
| AIDA: Automated analog IC design flow from circuit level to layout R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta 2012 International Conference on Synthesis, Modeling, Analysis and …, 2012 | 42 | 2012 |
| AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation N Lourenço, R Martins, A Canelas, R Povoa, N Horta Integration 55, 316-329, 2016 | 33* | 2016 |
| Floorplan-aware analog IC sizing and optimization based on topological constraints N Lourenço, A Canelas, R Póvoa, R Martins, N Horta Integration 48, 183-197, 2015 | 32 | 2015 |
| AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation R Martins, N Lourenço, A Canelas, R Póvoa, N Horta 2015 International Conference on Synthesis, Modeling, Analysis and …, 2015 | 30 | 2015 |
| Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction N Lourenço, R Martins, N Horta 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 30 | 2015 |
| Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates R Martins, N Lourenço, N Horta Expert Systems with Applications 42 (23), 9137-9151, 2015 | 25 | 2015 |
| Automatic analog IC sizing and optimization constrained with PVT corners and layout effects N Lourenço, R Martins, N Horta Springer International Publishing, 2017 | 24 | 2017 |
| Electromigration-aware analog Router with multilayer multiport terminal structures R Martins, N Lourenco, A Canelas, N Horta Integration 47 (4), 532-547, 2014 | 23 | 2014 |
| Electronic design automation of analog ics combining gradient models with multi-objective evolutionary algorithms FAE Rocha, RMF Martins, NCC Lourenço, NCG Horta Springer Science & Business Media, 2013 | 19* | 2013 |
| Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop R Martins, N Lourenço, F Passos, R Povoa, A Canelas, E Roca, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 16 | 2018 |
| Analog Integrated Circuit Design Automation R Martins, N Lourenço, N Horta Springer, 2017 | 15 | 2017 |
| LC-VCO automatic synthesis using multi-objective evolutionary techniques R Póvoa, R Lourenço, N Lourenço, A Canelas, R Martins, N Horta 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 293-296, 2014 | 15 | 2014 |
| Electromigration-aware and IR-drop avoidance routing in analog multiport terminal structures R Martins, N Lourenço, A Canelas, N Horta 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 15 | 2014 |
| LAYGEN II: Automatic analog ICs layout generator based on a template approach R Martins, N Lourenço, N Horta Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012 | 15 | 2012 |
| Many-objective sizing optimization of a class-C/D VCO for ultralow-power IoT and ultralow-phase-noise cellular applications R Martins, N Lourenço, N Horta, J Yin, PI Mak, RP Martins IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 69-82, 2018 | 12 | 2018 |
| Current-flow and current-density-aware multi-objective optimization of analog IC placement R Martins, R Povoa, N Lourenço, N Horta Integration 55, 295-306, 2016 | 12 | 2016 |
| Single-stage amplifier biased by voltage combiners with gain and energy-efficiency enhancement R Povoa, N Lourenço, R Martins, A Canelas, NCG Horta, J Goes IEEE Transactions on Circuits and Systems II: Express Briefs 65 (3), 266-270, 2017 | 11 | 2017 |
| Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations A Canelas, R Martins, R Póvoa, N Lourenço, N Horta 2016 13th International Conference on Synthesis, Modeling, Analysis and …, 2016 | 11 | 2016 |
| Single-stage OTA biased by voltage-combiners with enhanced performance using current starving R Povoa, N Lourenço, R Martins, A Canelas, N Horta, J Goes IEEE Transactions on Circuits and Systems II: Express Briefs 65 (11), 1599-1603, 2017 | 10 | 2017 |
Nuno LourençoInstituto de Telecomunicações (IT)Email confirmado em lx.it.pt
