| LAYGEN II—automatic layout generation of analog integrated circuits R Martins, N Lourenco, N Horta Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2013 | 57 | 2013 |
| AIDA: Automated analog IC design flow from circuit level to layout R Martins, N Lourenço, S Rodrigues, J Guilherme, N Horta Synthesis, Modeling, Analysis and Simulation Methods and Applications to …, 2012 | 37 | 2012 |
| Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction N Lourenço, R Martins, N Horta Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 …, 2015 | 28 | 2015 |
| Floorplan-aware analog IC sizing and optimization based on topological constraints N Lourenço, A Canelas, R Póvoa, R Martins, N Horta Integration, the VLSI journal 48, 183-197, 2015 | 28 | 2015 |
| Laygen ii: automatic analog ics layout generator based on a template approach R Martins, N Lourenço, N Horta Proceedings of the 14th annual conference on Genetic and evolutionary …, 2012 | 27* | 2012 |
| AIDA: Robust layout-aware synthesis of analog ICs including sizing and layout generation R Martins, N Lourenço, A Canelas, R Póvoa, N Horta Synthesis, Modeling, Analysis and Simulation Methods and Applications to …, 2015 | 22 | 2015 |
| AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation N Lourenço, R Martins, A Canelas, R Póvoa, N Horta Integration, the VLSI Journal 55, 316-329, 2016 | 21* | 2016 |
| Electromigration-aware analog Router with multilayer multiport terminal structures R Martins, N Lourenco, A Canelas, N Horta Integration, the VLSI Journal 47 (4), 532-547, 2014 | 21 | 2014 |
| Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates R Martins, N Lourenço, N Horta Expert Systems with Applications 42 (23), 9137-9151, 2015 | 16 | 2015 |
| Enhanced AIDA’s Circuit-Level Optimization Kernel FAE Rocha, RMF Martins, NCC Lourenço, NCG Horta Electronic Design Automation of Analog ICs combining Gradient Models with …, 2014 | 15* | 2014 |
| LC-VCO automatic synthesis using multi-objective evolutionary techniques R Povoa, R Lourenco, N Lourenco, A Canelas, R Martins, N Horta Circuits and Systems (ISCAS), 2014 IEEE International Symposium on, 293-296, 2014 | 9 | 2014 |
| A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis F Rocha, N Lourenço, R Povoa, R Martins, N Horta Evolutionary Computation (CEC), 2013 IEEE Congress on, 2781-2788, 2013 | 8 | 2013 |
| Analog circuit design based on robust POFs using an enhanced MOEA with SVM models N Lourenço, R Martins, M Barros, N Horta Analog/RF and Mixed-Signal Circuit Systematic Design, 149-167, 2013 | 8 | 2013 |
| Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects N Lourenço, R Martins, N Horta Springer, 2017 | 7* | 2017 |
| Current-flow and current-density-aware multi-objective optimization of analog IC placement R Martins, R Povoa, N Lourenco, N Horta Integration, the VLSI Journal 55, 295-306, 2016 | 6 | 2016 |
| Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations A Canelas, R Martins, R Póvoa, N Lourenço, N Horta Synthesis, Modeling, Analysis and Simulation Methods and Applications to …, 2016 | 6 | 2016 |
| Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures R Martins, N Lourenço, A Canelas, N Horta Proceedings of the conference on Design, Automation & Test in Europe, 10, 2014 | 6 | 2014 |
| Routing analog ICs using a multi-objective multi-constraint evolutionary approach R Martins, N Lourenco, N Horta Analog Integrated Circuits and Signal Processing 78 (1), 123-135, 2014 | 6 | 2014 |
| Analog Integrated Circuit Design Automation R Martins, N Lourenço, N Horta Springer, ISBN, 2017 | 4 | 2017 |
| Synthesis of LC-Oscillators Using Rival Multi-Objective Multi-Constraint Optimization Kernels R Póvoa, R Lourenço, N Lourenço, A Canelas, R Martins, N Horta Performance Optimization Techniques in Analog, Mixed-Signal, and Radio …, 2015 | 4 | 2015 |
Nuno LourençoInstituto de Telecomunicações (IT)Email confirmado em ist.utl.pt
