Farimah Farahmandi
Citado por
Citado por
Pre-silicon security verification and validation: A formal perspective
X Guo, RG Dutta, Y Jin, F Farahmandi, P Mishra
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
Trojan localization using symbolic algebra
F Farahmandi, Y Huang, P Mishra
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 591-597, 2017
Groebner basis based formal verification of large arithmetic circuits using gaussian elimination and cone-based polynomial extraction
F Farahmandi, B Alizadeh
Microprocessors and Microsystems 39 (2), 83-96, 2015
Hardware Trojan detection using ATPG and model checking
J Cruz, F Farahmandi, A Ahmed, P Mishra
2018 31st international conference on VLSI design and 2018 17th …, 2018
Automated Test Generation for Debugging Arithmetic Circuits
F Farahmandi, P Mishra
Design Automation and Test in Europe (DATE), 2016
Directed test generation using concolic testing on RTL models
A Ahmed, F Farahmandi, P Mishra
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Automated test generation for debugging multiple bugs in arithmetic circuits
F Farahmandi, P Mishra
IEEE Transactions on Computers 68 (2), 182-197, 2018
Defense-in-depth: A recipe for logic locking to prevail
MT Rahman, MS Rahman, H Wang, S Tajik, W Khalil, F Farahmandi, ...
Integration 72, 39-57, 2020
Scalable hardware Trojan activation by interleaving concrete simulation and symbolic execution
A Ahmed, F Farahmandi, Y Iskander, P Mishra
2018 IEEE International Test Conference (ITC), 1-10, 2018
Automated debugging of arithmetic circuits using incremental gröbner basis reduction
F Farahmandi, P Mishra
2017 IEEE International Conference on Computer Design (ICCD), 193-200, 2017
System-on-Chip Security: Validation and Verification
F Farahmandi, Y Huang, P Mishra
Springer Nature, 2019
Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks
A Nahiyan, F Farahmandi, P Mishra, D Forte, M Tehranipoor
IEEE Transactions on Computer-aided design of integrated circuits and …, 2018
FSM anomaly detection using formal analysis
F Farahmandi, P Mishra
2017 IEEE International Conference on Computer Design (ICCD), 313-320, 2017
Cost-effective analysis of post-silicon functional coverage events
F Farahmandi, R Morad, A Ziv, Z Nevo, P Mishra
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Post-Silicon Validation and Debug
P Mishra, F Farahmandi
Springer International Publishing, 2019
Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation
F Farahmandi, P Mishra, S Ray
Design Automation and Test in Europe, 2016
Effective combination of algebraic techniques and decision diagrams to formally verify large arithmetic circuits
F Farahmandi, B Alizadeh, Z Navabi
VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on, 338-343, 2014
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
MS Rahman, A Nahiyan, S Amir, F Rahman, F Farahmandi, D Forte, ...
IACR Cryptol. ePrint Arch. 2019, 946, 2019
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation
A Nahiyan, J Park, M He, Y Iskander, F Farahmandi, D Forte, ...
ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020
Hardware Trojan Detection Schemes Using Path Delay and Side-Channel Analysis
F Farahmandi, Y Huang, P Mishra
System-on-Chip Security, 221-271, 2020
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